搜索资源列表
count16
- count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
BCDcounter-piture
- BCD counter Dg ewgt wee rwh wer w-BCD counter Dg ewgt wee rwh wer w
part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
Trafficlight
- 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间； 因为各状态持续时间不一致，所以上述计数器应置入不同的预置数； 倒计时计数值输出至二个数码管显示； 程序共设置4个进程： ① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号； ② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code c
BCD.~(2).SCHDOC.Zip
- 这是二进制计数器的一部分程序，大家也可以在AD上面看。-This is part of binary counter procedures, we can also see AD above.
freqm
- a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
7BCDcountercode
- 7 BCD counter code -7 BCD counter code7 BCD counter code
bcd_updown_counter2
- It is a simple 4-digit bcd up down counter written in verilog
xq_Test7
- VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
Counter
- 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
VHDL-3BCD
- 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new cou
BCD-counter
- 一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. -A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output s
bcd
- it shows bcd counter
baseed-on-EDA-of-three-BCD-counter
- 基于EDA的三位BCD计数器，实现从0到999的计数功能-based on EDA of three BCD counter
BCD-program
- up/down BCD counter
BCD counter( state machine)
- a vhdl source code for BCD
bcd counter
- Binary counter design in verilog
4位BCD计数器
- 用Verilog语言编程实现4位BCD计数器的功能(Write the programm with Verilog language to implement the function of 4 - bit BCD counter.)