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Source.rar
- PWM Verilog源代码，可以通过仿真测试,PWM Verilog source code, can be tested through simulation
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
lai_PWM
- FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
pmw2ppm
- Vhdl code PPM to pwm converte
pwm_gen
- PWM _Generator VHDL code
FPGA_SOPC_PWM
- 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm.
PWM_GEN
- 这是Altera PWM生成的一个实例。包含project文件，源代码，仿真文件。经过验证，实际可用。-This is an example of Altera PWM generated. Contains the project files, source code, simulation files. After verification, the actual available.
test4
- 用 vhdl 语言实现的 32个 条目的 ARP-using vhdl language to realize ARP protocol with 32 entries
pwm
- PWM脉冲产生代码，程序采用VHDL硬件描述语言！很有参考价值-PWM pulse generation code, the program using VHDL hardware descr iption language! Useful reference
pwm_timer
- PWM和Timer的FPGA实现，文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.
PWM
- PWM Source Code in VHDL For FPGA Devices
pwm
- FPGA控制的 PWM LED程序 较为复杂 有助于新手进阶参考-FPGA PWM LED control is more complicated procedures will help novices Advanced Reference
PWM
- This a PWM (pulse-width modulation scheme code in VHDL)-This is a PWM (pulse-width modulation scheme code in VHDL)
samlecode.vhdl
- This document lists the basic function of a vhdl code including the entity and ending with archetecture. Also it has a sample code of pwm vs sigma delta signals output.
samlecode.vhdl
- THis code describes how to use the pwm singal generator and how to generate this using VHDL>
pwm
- 适合初学者对PWM调制的学习，解释比较明确，由于来元于核心程序，功能强大-Enables the keyboard scan code in Verilog source code, clear for beginners Comments
PWM
- 基于FPGA的PWM的演示实验和VHDL的演示实验代码-FPGA-based VHDL PWM demonstration experiments and demonstration experiment code
PWM
- VHDL code for PWM Generator with Variable Duty Cycle