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verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
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一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
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verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
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This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
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卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
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应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
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卷积交织的地址生成器，通过编译，很好的代码，珍藏-Convolutional Interleaver address generater
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卷积编码的VHDL代码，公司内部资料，不是个人随便编写的-VHDL code of convolutional encoding
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convolutional encoder vhdl code, rate 1/2, k=3
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viterbi decoder with convolutional encoder
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vhdl code for convolutional encoder
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实现（2，1，7）卷积编码以及相应的viterbi译码-(2,1,7) convolutional code and the corresponding Viterbi decoding
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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卷积码（2，1，3）编码过程。代码清晰简单，对应人民邮电版《通信原理》中卷积码编码过程-Convolutional code (2,1,3) encoder. Code is clear and straightforward, Telecommunications for the corresponding version of " Communication Principle" in the process of convolutional coding
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将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
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OFDM的FPGA实现 内含卷积编码 交织，频偏检测 完整的OFDM实现代码 -The FPGA contains OFDM convolutional coding to achieve interleaving, OFDM frequency offset detecting the full implementation code
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卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
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(2,1,7)viterbi convolutional code encoding, decoding, debugging through, you can directly use
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convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
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