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S3C6410X_Type_Circuit_Design_Guide_rev1.00
- S3C6410 線路設計時一定要參考的文件,尤其是DDR Layout guide一定要看.以免開發出的板子不能動.-S3C6410 circuit design must read this documents, especially DDR Layout guide. To avoid your board can not run in high speed.
OXE800SE_OXE800DSE
- SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM c
ddr
- 关于ddr sdram的一篇不错的文章，讲得挺详细的。-a good paper about ddr sdram，teaching you how to use ddr sdram.
DDRSDRAM
- DDR SDRAM设计及调试经验总结.pdf
K3(Hi3611)GuideLine
- K3(Hi3611) 多媒体处理器研发指导手册(华为内部47页研发文档)-K3 (Hi3611) multimedia processor developed guidelines (Huawei R & D within the 47 documents)
DDRdesigen.pdf
- DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
ug230.pdf
- The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific fe
ddr2.pdf
- JEDEC DDR 2 memory interface specification document
SSTL_1V8_JESD8-15A
- ddr接口电气标准，jdec sstl_3，pdf文档-jdec sstl 3.3v spec
ALI_M1621(71)
- M1671 - P4 Super North Bridge – CPU, AGP, PCI and Memory Controller The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit architecture optimized for CPU bus, DDR and AGP4X
Allwinner_V3s_Datasheet_V1.0.pdf
- 全志v3s的datasheet。详细的寄存器说明。 全志v3s介绍：内置64M ddr内存，qfp封装(V3s of datasheet. Detailed register instructions. Whole chronicles v3s introduction: built in 64M DDR memory, QFP package)
JESD79-5 DDR5 Spec Early Draft Rev0.1.pdf
- JEDC DDR-5 Standard. DDR-5 标准。(JEDC DDR-5 Standard. JESD79-5 DDR5 Spec Early Draft Rev0.1)