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LED_clock_quartus
- 用VHDL语言实现数显时钟，devid200.vhd为分频模块，scan.vhd为LED扫描模块，timecount.vhd为计数模块-VHDL digital clock, devid200.vhd for frequency module, scan.vhd for LED scanning module, timecount.vhd for counting module
VerilogDHL_clock
- 新来匝道穿上别人写的基于vhd的数字时钟很好大家看看啊，很规范的哦。-New ramp to wear someone else wrote vhd on the digital clock very well take a look at the ah, oh, very norms.
61EDA_D1077
- 数字钟电路原理图程序清单 ********顶层程序描述*********** 程序：TIMER_SET.VHD-Digital clock circuit schematic process procedures described in the top of the list of******************* procedures: TIMER_SET.VHD
LEDVHDL
- 8.2 LED控制VHDL程序与仿真 本节分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。 1. 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd。 --功能：译码输出模块，LED为共阳接法。 --最后修改日期：2004.3.24。 -8.2 LED control and simulation of VHDL procedures introduced in this section of the LED using FPGA st
3FSK.vhd
- 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
Digitalclock
- 数字钟：好刻录机大哥和旅客的 得利卡刚和旅客的将离开对方非公开了就噶了空间的快乐记录卡就够了看见了健康的的啊看来固定价格两科噶及的旅客；攻击力看过个 啊的非公开了骄傲的噶的了科技是-Digital clock: a good writer and passenger Delica brother and visitors will just leave the other side closed the space on the Karmapa and the joy of memory car
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module