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多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
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用verilog语言编写的按键消抖程序。通过下降沿检测法可以判断出是否按键。压缩包内也包含此按键消抖程序的modelsim仿真文件。-Verilog language with key debounce process. By falling edge detection method can determine whether the key. This compressed package also contains procedures for key debounce modelsim
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edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
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verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
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刚写的verilog 程序，控制直流电机正反转，具有严格的按键消抖函数，采用脉冲边沿检测法，防止误触发！-Just write verilog program to control the DC motor reversing, with strict key debounce function, pulse edge detection method, to prevent false triggering! ! ! Beginner EDA, if insufficient, please
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verilog的边沿检测技术，在fpga信号处理中应用相当的大,这也是一门艺术-the the verilog edge detection technology, in fpga signal processing is quite large, and this is an art
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边沿检测电路的程序，对于学习FPGA的语言非常重要，采用verilog语言编写。-Edge detection circuit program is very important for language learning FPGA using Verilog language.
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Verilog HDL边沿检测主要有上升沿和下降沿检测-Verilog HDL edge detection are rising and falling edge detection
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用verilog实现sobel边缘检测算法-sobel edge detection with verilog language
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Verilog脉冲边沿检查，此代码包含完整的工程，利用quartus软件可以直接运行仿真。-Verilog edge of pulse examination, this code contains the complete engineering, quartus software can be used to directly run the simulation.
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sobel edge detection using verilog code
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verilog code for edge detection logic
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基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
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脉冲边沿检测法的按键消抖程序，使用Verilog编写(Key edge dithering program with pulse edge detection method)
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波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
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通过纯HDL逻辑实现,对ov7725摄像头进行图像采集,存储,处理,包括中值滤波,边缘检测等经典图像算法实现(Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.)
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由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
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