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用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计,采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
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DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
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用VHDL求rsa加密系统的密钥D(辗转相除法)-Using VHDL for rsa key encryption system D(Division algorithm)
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高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
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在ISE平台上,利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
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A simple XOR encryption using verilog.
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基于FPGA的AES算法实现,使用verilog语言实现。本模块只包含解密过程,没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
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此例程是基于FPGA的USB控制器实例,主要功能为通过FPGA芯片控制USB芯片,实现开发板和PC机之间的USB接口数据通信,来模拟一个硬件加密设备的功能。用Verilog语言实现。-This routine is an instance of the USB controller based on FPGA, the main function is to control USB chip by the FPGA chip, implement the USB interface for da
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主要实现使用verilog HDL语言实现AES的加密算法-Main implementation using verilog HDL language implementation of AES encryption algorithm
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verilog实现的rsa加解密系统,包括大素数生成算法,包含测试文件。-rsa encryption system using verilog, including large prime number generation algorithms, including test file.
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用verilog实现的DES(Data Encryption Standard数据加密标准),把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
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利用verilog语言实现了SHA-1机密算法,具体算法与加密芯片ds28e01一致。-Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.
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用verilog语言实现加密芯片DS28E01的调用操作命令。-Using Verilog language to achieve the encryption chip DS28E01 call operation commands.
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sm4加密算法fpga实现,采用verliog语言(SM4 encryption algorithm FPGA implementation, using verliog language)
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aes 256位 算法 加密程序,使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)
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