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grlib-eval-1.0.2a.tar
- The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor inde
leon3-altera-ep2s60-ddr
- The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor in
i2c
- 这是NOIS II的IP CORES I2C是个好东西啊 是FPGA学习的好东西
vga_lcd
- 这个是VGA的核是NOIS开发时使用的IP CORES 在FPGA的开发中使用的比较多
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
在ISE下调用计数器IP核
- 非常简单的计数器，在ISE下调用计数器IP核，使用verilog开发得到的。-Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
xapp859_rtl
- xilinx PCIE IP核 包括ddr2 memory interface ML555开发板-xilinx PCIE IP cores containing ddr2 memory interface can be used on ML555 development kit
15-IP-core
- 15个免费的IP核 IP核源代码 -15 IP cores
USB_xilinx
- USB应用的IP核心，需要深入了解 核心的行为。建立本 诀窍是大大简化了全面 参考应用。-Application of IP-Cores requires in-depth knowledge of the core’s behavior. Building up this know-how is greatly simplified by comprehensive reference applications.
IntegrationofSystem-On-ChipSimulationModels
- SOC仿真模型的整合 丹麦技术大学 硕士论文 通过SystemC来建立SOC仿真模型-Integration of System-On-Chip Simulation Models Technical University of Denmark Master Thesis Reaching deep sub-micron technology within the near future makes it possible to implement comple
8051code
- VHDL源码 8051+IP内核 在xilinx环境仿真运行 不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface
ip_core
- 一些FPGA上用的到的IP核,种类非常全,开发小的ASIC基本上够用了-To use some of the FPGA IP cores, species are very full, the development of ASIC basically small enough
ise-ip-core
- IP核包括硬IP与软IP。调用IP核能避免重复劳动，大大减轻设计人员的工作量。-IP cores, including hard IP and soft IP. IP calls to avoid duplication of nuclear energy, thus greatly reducing the workload of the designer.
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
I2C-Controller-IP
- 实现通过I2C来控制IP内核的简易程序，适合新手学习使用-Achieved through the IC to control the IP cores to the simplified procedure, suitable for beginners learning to use
FPGA-floating-Point-IP-cores
- Taking Advantage of Advances in FPGA floating-Point IP cores -Taking Advantage of Advances in FPGA floating-Point IP cores
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
chu_ip_drv
- It contains the C driver (.c and .h) files of IP cores in Parts III and Part IV. Since the driver files are not integrated with HAL, the corresponding files must be manually copied to the software application project directory when a core is used i
ip-cores-video_controller_jpeg_encoder
- ip-cores-video_controller_jpeg_encoder