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Ucore是一个很小的适于学习的操作系统
- Ucore是一个很小的适于学习的操作系统，此“麻雀”包含虚存管理、进程管理、处理器调度、同步互斥、进程间通信、文件系统等主要内核功能，总的内核代码量（C+asm）不会超过5K行。充分体现了“小而全”的指导思想。 这是ucore实验6：文件系统。通过完成本次实验，希望能达到以下目标：了解基本的文件系统系统调用的实现方法；了解一个基于索引节点组织方式的Simple FS文件系统的设计与实现；了解文件系统抽象层-VFS的设计与实现。文件中包括源代码和实验指导书。-Ucore is a small
shiyan6-B 计算机图形学实验6 常用曲面和曲线的生成算法
- 计算机图形学实验6 常用曲面和曲线的生成算法 包括（三次B样条曲线算法）-Computer Graphics Lab 6 common surfaces and curves, including generating algorithm (cubic B-spline algorithm)
嵌入式网络协议Lwip0.6
- lwIP is a small independent implementation of the TCP/IP protocol suite that has been developed by Adam Dunkels at the Computer and Networks Architectures (CNA) lab at the Swedish Institute of Computer Science (SICS). -lwIP is a small indepen
RTDSPLab1-6
- INTRODUCTION TO DSP PROCESSORS LABORATORY INSTRUCTION LAB GUIDLINES
keygen8.6
- Labview 8.6 注册机，已验证， 下灾之后直接打开。-Zhuceji Labview 8.6 has been verified, directly under the open after the disaster.
Lab6-Starter0
- lab 6 is also very important
wrwar
- EE367 Lab 6 Creating a FIR filter in VHDL
ac_analysis_lab_6
- solution lab 6 about ac analysis
MicrosoftC++6
- Key features and lab exercises to familiarize new users to the Visual environment
shiyan6-double-Bezier
- 计算机图形学实验6 常用曲面和曲线的生成算法 包括（双三次Bezier曲面算法）-Computer Graphics Lab 6 common surfaces and curves, including generating algorithm (bi-cubic Bezier surface algorithm)
graphics-lab
- 计算机图形学上机实验指导，OPENGL基础， 2.计算机图形学实验 (二) – OPENGL变换3.计算机图形学实验 (三) - 画线、画圆算法的实现 4.计算机图形学实验（四） - 高级OPENGL实验 5.计算机图形学实验（五）- 高级OPENGL实验 6.计算机图形学实验 (六) –-Computer graphics on experiments guidance, OPENGL based on 2 Computer Graphics experiments (B)-
CSC323-LAB-6-Currency-Conversion
- University of New Brunswick. Engineering CSC323. Programing and Algorithm. LAB # 6: Currency Converter. Written in Java.
6
- DSP course lab 6 MATLAB
JOS-all-with-lab-answers
- MIT 6.828 JOS Lab，操作系统实习完整代码（包括部分Challenge实现），以及Lab问题答案。-MIT 6.828 course, JOS lab complete source code with answers for lab questions and some of the challenges.
lab6_assignment
- lab 6 assignment for matlab
FPGA-Train
- FPGA基础培训，包括： FPGA基本架构 Xilinx工具流程 实验1：Xilinx工具流程演示 实验2：架构向导和PACE 实验3：全局时序约束 实验4：合成技术 实验5：CORE Generator系统 实验6：利用ChipScope-PRO-Basic FPGA Architecture Xilinx Tool Flow Lab 1: Xilinx Tool Flow Demo Architecture Wizard and PACE L
LAB-6
- Communication Systems Lab 6
lab 6
- Goals and Background This lab introduces you to a symbolic debugger to use with Java programs. The debugger is part of the free Eclipse IDE. Eclipse is not installed on aludra, but is available on the campus lab machines. However, you may want to
lab 6
- Data Structure Lab 6
LAB#6 (1)
- 設計一個具有一個輸入端x 與一個輸出端z 的同步序向邏輯電路，當電路偵測到輸入序列中的1 總數為3 的倍數(即0、3、6?) 時，即輸出一個1 脈波於輸出端z。(To design a synchronous sequential logic circuit with an input x and an output z, a 1-pulse is output when the circuit detects a total of 1 in the input sequence as a mu