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decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
LDPC_Behavioral_VHDL
- 用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
H_2048x4096
- LDPC 码二进制规则码生成矩阵2048*4096，效果很理想-LDPC code rules binary code generated matrix 2048* 4096, the effect is very satisfactory
H_512x1024
- LDPC 码二进制规则码生成矩阵512*1024，效果很理想-LDPC code rules binary code matrix to generate 512* 1024, the effect is very satisfactory
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
ldpc_c_code
- LDPC码在基于BP (Belief Propagation) 的迭代译码相结合的条件下具有逼近Shannon 限的性能，是继turbo 码后在纠错编码领域又一重大进展。压缩文件中给出了LDPC在高斯信道下的c程序。-LDPC codes based on BP (Belief Propagation) Iterative Decoding of combining conditions with performance approaching Shannon limit on the heel
ldpcverilog
- verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror
ps_decoder3_12_80_mod
- PS-LDPC码译码器的Verilog程序-PS-LDPC code decoder of the Verilog program
the-decoding-algorithm-of-ldpc
- ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等-introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum
ldpc-encode
- 深空通信中AR4JA码编码的研究与实现，ＡＲ４ＪＡ码是ＬＤＰＣ码的一种，文件中是Ｖｅｒｉｌｏｇ语言的硬件实现。-Research and Implementation of the Deep Space Communications AR4JA coding, AR4JA code LDPC codes a hardware implementation of the Verilog language file.
dvb_s2_ldpc_decoder_latest.tar
- 用于数字电视机顶盒的DVB-S2的LDPC编码的解码模块，verilog代码-For digital TV set-top boxes of DVB- S2 LDPC coding, decoding module of verilog code
vnp
- 移动通信技术中信道编码的LDPC码的VNP的Verilog hdl 实现-Channel coding of mobile communication technology LDPC code VNP realization of Verilog hdl
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
verilog_rtl
- 关于LDPC解码的verilog程序，包含设计代码和验证环境-LDPC decoding on verilog procedures, including the design code and verification environment
XOR_tree
- This source code is a check node unit for LDPC decoder. The language is Verilog HDL.
e60a9bd4-ef5c-4c89-bfb3-9da40d5e4aba
- 低密度校验码 ，很好用的代码，功能已经实现编码和译码(Low density parity check code, very good code, the function has been achieved encoding and decoding)
gray_counter_vhd
- ldpc verilog code has been descr ipted in this program
src
- 用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)
LDPC
- LDPC编码的硬件代码,可在modelsim上验证(verilog code for ldpc encode)