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all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
spi_master
- SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer
top_module
- AES Encryption Algorithm.... This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module-AES Encryption Algorithm.... This Module gives the basic overview to
VHDLtraining
- The basic concepts of VHDL language 1.1 Data types and data objects declared 1.2 VHDL descr iption of the syntax 1.3 Class design 1.4 functions, procedures and packages 1.5 Issues and discussion 1.6 References-The basic concepts of VHDL l
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
IEEE---IEEE-Standard-VHDL-Mathematical-Packages.r
- IEEE - IEEE Standard VHDL Mathematical Packages
6_Sets_of_8051_VHDL_Verilog
- it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scr ipts, pdfs, netlists etc. and a MIPS IP package
ADC_DAC_FMF_converters_vhdl.tar
- This library contains VHDL 1076 models of analog to digital and digital to analog converters. They use the VITAL packages but are not VITAL compliant.
doc
- this defined as osvvm packages pdf it is helpful in vhdl verification by using these packages we can verify vhdl code - this is defined as osvvm packages pdf it is helpful in vhdl verification by using these packages we can verify vhdl code
osvvm-packages
- osvvm packages that is helpful for vhdl verification
AlertLogPkg
- osvvm alert packages that is helpful for vhdl verification
CoveragePkg
- osvvm coverage packages that is helpful for vhdl verification
Lab5
- In this lab you will combine the techniques you learned in the previous labs and new ones to design an electric wheel of fortune on the Nexys-2 board. New coding techniques introduced in this lab are building vhdl modules using packages and procedure
Kisi Kisi -20171008
- It is a long established fact that a reader will be distracted by the readable content of a page when looking at its layout. The point of using Lorem Ipsum is that it has a more-or-less normal distribution of letters, as opposed to using 'Content her