搜索资源列表
rs-codec-8-16
- 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Crack_QII72_b151
- Crack_QII72_b151 is quatus ii used for fpga.
taxi
- 在quatus下用VerilogHDL语言编写，实现出租车计价器功能
RS232
- quatus II 环境下vhdl实现RS232功能
Quartusii
- 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程，对初学者很有帮助。
seven_segment
- 以quatusⅡ为平台，用HVDL语言实现7段数码管译码器的功能。
LOCK
- 以quatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。
DE2_with_VGA_LCM
- altera de2 开发板 vga lcd控制quatus 工程
sopc_led
- de2板上的led显示程序，最简单的nios测试程序，可以实现de2板上的两个小灯的闪烁，用quatus ii定置sopc系统！-de2 board led display program, the simplest nios test procedures can be achieved in two de2 board flashing lights, and quatus ii set sopc system!
PIPE_LINING_CPU_TEAM_24
- 采用quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
Digital_filterin_code
- MATLAB辅助设计数字滤波器源代码，quatus II 实现！-MATLAB-aided design of digital filter source code, quatus II implementation!
FPGA_CPLD
- 其中详细的介绍了如何用quatus2软件来实现FPGA和CPLD的综合设计-Which describes in detail how to achieve quatus2 software integrated FPGA and CPLD design
acpu
- EDA平台，CPU模拟机，quatus II软件运行-a simple CPU based on EDA
Quartus_Common_Error_And_Warning_Analyze
- quatus常见错误汇总与分析 该文章来源 :一是来自网上几处出处的汇总 二是来自作者本人应用过程中遇到的问题。 可以帮助大家解决烦人的quartus警告和error 仅供参考 -Summary and analysis of common mistakes quatus the article Source: First, a summary of provenance from the Internet a few second is from the author
vhdl_digital_output
- Digital signal output module... tested by Altera MaxPlusII or quatus -Digital signal output module... tested by Altera MaxPlusII or quatus II
vhdl_edge_ris
- rise edge detecting some signal module... tested by Altera MaxPlusII or quatus -rise edge detecting some signal module... tested by Altera MaxPlusII or quatus II
vhdl_i2c_slave
- Inter Intergrate Circuit slave module... tested by Altera MaxPlusII or quatus -Inter Intergrate Circuit slave module... tested by Altera MaxPlusII or quatus II
vhdl_pwm_drv
- Pulse Width Modulation signal generation output module... tested by Altera MaxPlusII or quatus -Pulse Width Modulation signal generation output module... tested by Altera MaxPlusII or quatus II
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or quatus II
keyboard_control
- 用verilog寫得鍵盤控制,可在quatus執行-Verilog is written with the keyboard control, the implementation of the quatus