搜索资源列表
FPGACPU
- FPGA RSIC CPU设计文档和源码是EDA中对CPU设计非常好用的程序
8051的内核(vhdl)
- 最完整最实用的8051的软核，用VHDL语言编写全部原代码，并有详细的注释介绍，对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced mult
rsic
- 这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现，希望对大家有帮助-This is my internship students of National Chiao Tung University in Shanghai to do when a single chip verilog code, and they hope to help you
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Pipelined_CPU
- 此程序是关于MIPS的RSIC架构的带有流水线功能的源码，对于RSIC_CPU的初学者在理解RSIC系统上有很大的帮助。-This program is about the RSIC architecture MIPS pipelined function with source code, for novices to understand the RSIC RSIC_CPU system is very helpful.
RSIC_CPU2
- 这是一个用verilog编写的RSIC CPU模型，几个必要的模块都已经齐全，有兴趣的可以再完善更多的功能-This is a verilog written RSIC CPU model, several necessary modules are already complete, are interested in more features can be further improved
myfirst_niosii
- Altera DE0-Nano 开发平台NiosII软核处理器RSIC。-Altera DE0-Nano development platform NiosII the soft core processor RSIC.
risc8_cpu_verilog
- 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as
RSIC
- 包含控制部分和逻辑运算部分的精简CPU，适合verilog的初学者(Ti's a CPU which contain the part of chontrol and Arithmetic logic,it's approximate for people who contact veriolg with short time)
GD32VF103用户手册
- GD32VF103系列器件是基于Nuclei Bumblebee处理器的32位通用微控制器，其中Bumblebee 处理器是基于RSIC-V架构指令集开发而来，以下简称RISC-V处理器。