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cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
counter
- 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed descr iption of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter
Register
- -- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data in
UpDownCounter
- an up down counter in verilog
UpDownConter
- an up down counter for AVR
UP.DOWN.HEX.COUNTER
- Up down counter for microchip ASM code tested
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga
bcd_updown_counter2
- It is a simple 4-digit bcd up down counter written in verilog
TB_Example_for_Students
- test bench for up down counter
counter
- a program for the up down counter with clk setting so that it can be ported directly on to fpga nexsys board
counter
- Source code of a up/down counter in VHDL
8bit_upDown_counter
- a simple 8 bit up/down counter, very handy and optimized
3digitUpDown16f84
- 3 digit up down pic counter
up-down-counter
- up down counter by verilog
up-down-counter
- BASCOM-AVR:递增递减计数器项目： 这是一个向上和向下计数器。这个项目包括两个红外传感器，该传感器连接到外部中断INT0和INT1。你可以使用任何感应器，甚至切换输入。-AVR Increment Decrement Counter Project: This is a up and down counter. this project consist of two infrared sensor that connected to Int0 and Int1 of Ext
counter
- Up Down counter FPGA, VHDL
PIC16F877-Up-Down-Counter-Code
- Documents about up-down countor
verilog-lfsr-updown-counter
- Verilog 8 bit LFSR Up-Down Counter
Up-down converter
- behavioural level program for up-down conter