搜索资源列表
div_3
- verilog 三分频器 并含仿真文件 波形-Verilog three dividers and documents containing waveform simulation
fre_division
- 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频
半整数分频器的实现（verilog）
- 半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！,fen pin qi
verilog-divider-code
- Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
n_evendivider
- 标签： Verilog 分频器 N倍奇数分频器.(Verilog) N_odd_divider.v / Verilog module N_odd_divider (-Labels: Verilog divider divider N odd times. (Verilog) N_odd_divider.v/Verilog module N_odd_divider (
quartus-work
- 基于FPGA的VERILOG的分频器的设计，10分频设计的源代码和设计思路-Based od FPGA
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
2
- 介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
AutoWashing
- 基于verilog-hdl的洗衣机自动控制电路，经下载仿真测试通过 附带时钟分频器-Verilog-hdl-based automatic control circuit of the washing machine, after download the simulation test
fdivision
- 基于verilog的分频器,以及相应的test bench-A frequency divider based on verilog
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
decimal_divison
- 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
fenpin
- 可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。(N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock.)
plj
- 2秒闸门时间频率计，以及一个分频器，使用FPGA及verilog语言实现(2 second gate time frequency meter)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
project code5
- 数控分频器的verilog代码在eda上实现(verilog for numerical control divider)
分频器
- 包括奇数分频和偶数分频的verilog和仿真文件代码