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《数字设计和计算机体系结构》一书MIPS verilog源码。
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Computer Architecture Handbook on Verilog HDL
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基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
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This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting
coding, including finite field arithmetic, (Generalized) Low-Density Parity-
Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to sever
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此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
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有效的并行编码器对于长BCH编码的 大家放心 真的号死后和很好评的-Area efficient parallel decoder architecture for long BCH codes
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This is a source code of 256 point fft architecture. This code is also available with opencores-This is a source code of 256 point fft architecture. This code is also available with opencores
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CAM is useful vhdl code to understand its architecture which helps to write any code
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一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
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本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和
程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入
利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种
九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
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Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
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基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
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this document explain the majors of VERILOG language in a very efficient and briefly manner.this is very useful to learn about hardware design and implementing them by FPGAs.
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MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
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计算机组成实验作业1，fpga开发板，verilog语言编写-Composition of experimental computer operating 1, fpga development board, verilog language
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计算机组成实验作业2，fpga开发板，verilog语言编写-Composition of experimental work computer 2, fpga development board, verilog language
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计算机组成实验作业3，fpga开发板，verilog语言编写-Composition of experimental computer operating 3, fpga development board, verilog language
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计算机组成实验作业4，fpga开发板，verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
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计算机组成实验作业5，fpga开发板，verilog语言编写-Composition of experimental computer operating 5, fpga development board, verilog language
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计算机组成实验作业6，fpga开发板，verilog语言编写-Composition of experimental computer operating 6, fpga development board, verilog language
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