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seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
mealymoore
- verilog project for mealy and moore
Verilog_hw_problem1---Copy
- this is a verilog program for a mealy machine
mealy
- MEALY fsm source code in vhdl, implemented on fpga
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
fsm
- verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
lab9_2
- 用verilog实现更高级的交通灯：增加*模式。实质上是对米粒状态机的掌握-An implementation in verilog on Mealy FSM
Ver_prog
- Verilog programs for trafficlight controller, dicegame, mealy,moore machines and universal shift register
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
soda_machine_mealyamoore
- soda_machine的一个有限状态机，用verilog描述，分别有moore和mealy,还提供了testbench.-soda_machine of a finite state machine, with verilog descr iption, respectively, moore and mealy, also provides a testbench.
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
Mealy_TrafficLight
- 基于FPGA交通控制器的Mealy状态机实现(Mealy state machine controller based on FPGA traffic)
4bit_mealy
- Mealy machine is a state machine whose output is determined by the current state and the current inputs.