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8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
speech
- 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
IFFT-RTL
- 本人自己写的可实现512点或64点IFFT算法的verilog硬件代码-the verilog code for IFFT algorithm
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
watch_dog_rtl_source
- Watchdog timer verilog RTL code
timer_rtl_source
- Timer verilog RTL code
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
rtl
- ddr controller in verilog-ddr controller in verilog...............
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
rtl
- SPI verilog RTL code
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
rtl
- LCD1602 Verilog 代码实现。包括数据读写，地址读写，初始化。支持4位总线格式。注意:此程序已经在ML506板子上验证过。本人花了好几天调试，开发出来的。值得推荐。-Verilog coding for LCD1602 display
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
the-verilog-source-code-of-8051-MCU
- 8051单片机的源代码,用verilog进行编写，包括测试文件-source code of 8051 MCU
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys