搜索资源列表
xapp288
- This the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions -This is the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
DecoderAudio
- 本程序为SDI的音视频分离Verilog程序，信号通过分离后，可以分离出视频和音频信号。-This procedure for the separation of SDI audio and video Verilog program, the signal after the separation, can be isolated video and audio signals.
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
SDI资料
- xilinx官方资料 学习sdi很好的入门资料(Xilinx official information, , a good introductory information for learning SDI)
sdi_audio
- sdi音频嵌入及解嵌代码,代码使用Verilog HDL语言(SDI audio embedding and decoding code, the code using Verilog HDL language)
SDI_controller
- 项目:用到FPGA驱动GV7600输出SDI信号，输出分辨率1920*1080p，首先，了解GV7600芯片的特性功能，按照bt1120协议传输10位Y，Cb，Cr数据；其次，我的项目中用的是10位通道分时复用传输Y，Cb，Cr数据；配置引脚很重要，当初verilog代码写好了，因为硬件引脚配置错误，导致调试一直不通；同时，sof文件也要一直更新(Based on FPGA to design the drive controller of GV7600)