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DDS_信号源
- dds 精确步进100HZ.拨码开关选择FSK,FM等功能.最高频率25M,da芯片9760.vhdl编写
THS5651是一款高速da转换器
- THS5651是一款高速da转换器，最高转换频率可到达100MBPS，该程序利用vhdl语言对THS5651进行控制,THS5651 is a high-speed da converter, the maximum conversion frequency can be arrived at 100MBPS, the use of vhdl language in the process control of the THS5651
6tapFIR.rar
- 6阶FIR+verliog+分布式算法（da）,6 bands FIR+ Verliog+ Distributed Arithmetic (da)
tlv5619_test.rar
- TLV5619是一款电压输出型的da转换器，该程序利用vhdl实现对TLV5619D的控制,TLV5619 is a voltage output type da converter, the program achieved using vhdl control TLV5619D
da.rar
- 利用可编程逻辑器件进行D/A和A/D控制接口的设计 ,The use of programmable logic device to carry out D/A and A/D control interface design
da
- FPGA控制daC2807的源文件，Verilog。附有简单文档-FPGA control daC2807 source, Verilog. A simple document
dac
- 这是一款用vhdl语言编写的对外部da芯片的控制程序，所用da转换芯片是TI公司的TLC5615.-This is a vhdl languages used on the external da chip control procedures, using da converter chip is TI
vhdl_code
- 基于FPGA的AD,da,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的vhdl源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, da, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. vhdl source code, all procedures have been debugging, need to take.
tlc5615
- TLC5615串行da的驱动接口,采用verilog编程-TLC5615 driver da serial interface using verilog programming
EP1C3_12_5_RSV
- 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用da在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using vhdl achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into da in ordinary oscilloscope can display.
01.ISE8.2
- 这个是我用的合众达试验箱里面的资料。合众达试验箱里面集成的是xilinx的virtex4，这个是在ise环境中审计的程序，包括led,da/ad转换实验，键盘实验，以及rtc读取和lcd显示等。-vhdl programs that used by xilinx virtex4
CPLD
- ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
high_speed_tap8_DDS
- 用verilog编写的高速8路并行dds模块，用于与高速da(1ghz或以上)接口产生任意频率正弦波，模块已经经过工程验证，用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the prod
vhdl_da
- 大量的vhdl程序实例，供大家参考学习，是学习vhdl的好书。-vhdl procedures for a large number of examples for your reference
AIC
- 使用FPGA/CPLD设置语音AD、da转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, da conversion chip AIC23, FPGA/
vhdlprogram
- 含有各类寄存器，AD和da转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and da converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
ADPCM
- APPCM算法和AD/da芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境-APPCM algorithm and AD/da chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。da芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
da
- FIR滤波器利用串行da算法实现16阶的，直接可用 ，用vhdl编程-Serial da FIR filter algorithm using 16 bands, directly available, vhdl programming
Verilog-hdlFPGA
- 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制vhdl程序与仿真，AD/da，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and vhdl simulation, AD/da, MASK, FSK, PSK, sine wave generator, and so the classi