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  1. acs

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  2. ACS for viterbi (r=1/2, pol=[133,171])
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-30
    • 文件大小:1.1kb
    • 提供者:sassou
  1. viterbi

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  2. 硬判决viterbi译码的硬件实现,通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:90.27kb
    • 提供者:Fengxiaodong
  1. ACS_Unit

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  2. ACS UNIT FOR VITERBI DECODER function: It will add-compare-select the branch matric hence it will help to find the minimum path matrics which is necessary for viterbi decoding-ACS UNIT FOR VITERBI DECODER function: It will add-compare-selec
  3. 所属分类:Communication

    • 发布日期:2017-11-12
    • 文件大小:8.75kb
    • 提供者:kushan
  1. acs

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  2. This an ACS unit which can be used in log-map algorithm as well as viterbi algorithm-This is an ACS unit which can be used in log-map algorithm as well as viterbi algorithm
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.4mb
    • 提供者:arulananthan
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