搜索资源列表
S3Demo
- 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS / 2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
xilinx user guide
- 教你如何设计使用timing
06529_xilinx
- XILINX的时序约束教程，详细的介绍了各种时序关系和约束-Timing Constraints Guide, a detailed introduction to the various temporal relations and constraints
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
ISE
- 介绍Xilinx公司FPGA/CPLD的集成开发环境——ISE软件的简单使用，该软件环境集成了FPGA的整个开发过程所用到的工具。主要介绍了用VHDL、VerilogHDL、原理图以及用ModelSim 仿真工具对设计进行功能仿真和时序仿真以及将数据流文件加载到FPGA等方面的内容。-Xilinx Inc. introduced FPGA/CPLD integrated development environment- ISE software simple to use, the softwa
TimingConstraint
- xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
ddr_verilog_xilinx
- xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
VGAbars_1016
- VGA Bar Generator generates VGA timing and outputs bars of fixed colors. Tested on Xilinx Spartan3 SP305 board and works fine.
FPGA_VGA_displaydoctum
- 使用 FPGA 控制 VGA 显示 相关知识介绍：包括 显示器术语 显示卡术语 VGA 时序设计 色彩原理 显示 源代码 相关测试图片-The use of FPGA control VGA display relevant knowledge, Introduction: terminology, including display graphics card design color theory terminology VGA timing related t
Advanced-Xilinx-FPGA
- Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™
timing_constraints_ug
- xilinx timing constrain file
Timing_constraints(Xilinx)
- 详细介绍FPGA的时序逻辑设计，简要介绍时序设置需要注意的要点与重点，set up time and hold time and so on -Details of the timing of FPGA logic design, timing set to note briefly the main points and key, set up time and hold time and so on
Xilinx-fpga
- xilinx时序约束的重要官方资料。非常有用-Xilinx timing constraints of important official material.
xilinx-timing-constrains
- ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助-In this file , global timing constraints is introduced very clearly. It can really helps
Xilinx-constraints-guide2
- xilinx时序约束指南，详细的说明和使用操作实例-xilinx timing constraints
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
Timing-Analyzer-Guide-3.1i
- Timing analyser for xilinx
xilinx_Timing_constraints
- Xilinx时序约束文档，包括什么情况下使用时序约束、为什么要时序约束、如何进行时序约束等。-Xilinx timing constraint document, including under what circumstances the use of timing constraints, why should the timing constraints, how to carry out the timing constraint.