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文件名称:UART_Verilog
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- 上传时间：2012-11-16
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文件大小：483.67kb
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Altera FPGA的UART通讯程序-Altera FPGA' s UART communication program
相关搜索： uart altera
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下载文件列表
uart_tb.v.bak
uart_tb.vcd
vsim.wlf
rtl_wrk/@rx/verilog.asm
rtl_wrk/@rx/_primary.dat
rtl_wrk/@rx/_primary.vhd
rtl_wrk/@tx/verilog.asm
rtl_wrk/@tx/_primary.dat
rtl_wrk/@tx/_primary.vhd
rtl_wrk/uart_tb/verilog.asm
rtl_wrk/uart_tb/_primary.dat
rtl_wrk/uart_tb/_primary.vhd
rtl_wrk/_info
modelsim.ini
run.do
Rx.v
Rx.v.bak
Tx.v
Tx.v.bak
uart_tb.v
rtl_wrk/@rx
rtl_wrk/@tx
rtl_wrk/uart_tb
rtl_wrk
uart_tb.vcd
vsim.wlf
rtl_wrk/@rx/verilog.asm
rtl_wrk/@rx/_primary.dat
rtl_wrk/@rx/_primary.vhd
rtl_wrk/@tx/verilog.asm
rtl_wrk/@tx/_primary.dat
rtl_wrk/@tx/_primary.vhd
rtl_wrk/uart_tb/verilog.asm
rtl_wrk/uart_tb/_primary.dat
rtl_wrk/uart_tb/_primary.vhd
rtl_wrk/_info
modelsim.ini
run.do
Rx.v
Rx.v.bak
Tx.v
Tx.v.bak
uart_tb.v
rtl_wrk/@rx
rtl_wrk/@tx
rtl_wrk/uart_tb
rtl_wrk
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