文件名称:ata_ip
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ATA接口的IP核,经过量产的验证,已经在quartus5.1下编译通过了.-ATA interface IP core, after volume production test in quartus5.1 compiler passed.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ata/bench/cvs/Entries
ata/bench/cvs/Repository
ata/bench/cvs/Root
ata/bench/cvs/Template
ata/bench/cvs
ata/bench/verilog/ata_device.v
ata/bench/verilog/cvs/Entries
ata/bench/verilog/cvs/Repository
ata/bench/verilog/cvs/Root
ata/bench/verilog/cvs/Template
ata/bench/verilog/cvs
ata/bench/verilog/tests.v
ata/bench/verilog/test_bench_top.v
ata/bench/verilog/wb_mast_model.v
ata/bench/verilog/wb_model_defines.v
ata/bench/verilog/wb_slv_model.v
ata/bench/verilog
ata/bench
ata/cvs/Entries
ata/cvs/Repository
ata/cvs/Root
ata/cvs/Template
ata/cvs
ata/doc/cvs/Entries
ata/doc/cvs/Repository
ata/doc/cvs/Root
ata/doc/cvs/Template
ata/doc/cvs
ata/doc/preliminary_ata_core.pdf
ata/doc/src/ata_core.doc
ata/doc/src/cvs/Entries
ata/doc/src/cvs/Repository
ata/doc/src/cvs/Root
ata/doc/src/cvs/Template
ata/doc/src/cvs
ata/doc/src
ata/doc
ata/rtl/cvs/Entries
ata/rtl/cvs/Repository
ata/rtl/cvs/Root
ata/rtl/cvs/Template
ata/rtl/cvs
ata/rtl/verilog/cvs/Entries
ata/rtl/verilog/cvs/Repository
ata/rtl/verilog/cvs/Root
ata/rtl/verilog/cvs/Template
ata/rtl/verilog/cvs
ata/rtl/verilog/ocidec-1/atahost_controller.v
ata/rtl/verilog/ocidec-1/atahost_pio_tctrl.v
ata/rtl/verilog/ocidec-1/atahost_top.v
ata/rtl/verilog/ocidec-1/atahost_wb_slave.v
ata/rtl/verilog/ocidec-1/cvs/Entries
ata/rtl/verilog/ocidec-1/cvs/Repository
ata/rtl/verilog/ocidec-1/cvs/Root
ata/rtl/verilog/ocidec-1/cvs/Template
ata/rtl/verilog/ocidec-1/cvs
ata/rtl/verilog/ocidec-1/revision_history.txt
ata/rtl/verilog/ocidec-1/ro_cnt.v
ata/rtl/verilog/ocidec-1/timescale.v
ata/rtl/verilog/ocidec-1/ud_cnt.v
ata/rtl/verilog/ocidec-1
ata/rtl/verilog/ocidec-2/atahost_controller.v
ata/rtl/verilog/ocidec-2/atahost_pio_actrl.v
ata/rtl/verilog/ocidec-2/atahost_pio_tctrl.v
ata/rtl/verilog/ocidec-2/atahost_top.v
ata/rtl/verilog/ocidec-2/atahost_wb_slave.v
ata/rtl/verilog/ocidec-2/cvs/Entries
ata/rtl/verilog/ocidec-2/cvs/Repository
ata/rtl/verilog/ocidec-2/cvs/Root
ata/rtl/verilog/ocidec-2/cvs/Template
ata/rtl/verilog/ocidec-2/cvs
ata/rtl/verilog/ocidec-2/revision_history.txt
ata/rtl/verilog/ocidec-2/ro_cnt.v
ata/rtl/verilog/ocidec-2/timescale.v
ata/rtl/verilog/ocidec-2/ud_cnt.v
ata/rtl/verilog/ocidec-2
ata/rtl/verilog
ata/rtl/vhdl/cvs/Entries
ata/rtl/vhdl/cvs/Repository
ata/rtl/vhdl/cvs/Root
ata/rtl/vhdl/cvs/Template
ata/rtl/vhdl/cvs
ata/rtl/vhdl/ocidec1/atahost_controller.vhd
ata/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec1/atahost_top.vhd
ata/rtl/vhdl/ocidec1/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec1/cvs/Entries
ata/rtl/vhdl/ocidec1/cvs/Repository
ata/rtl/vhdl/ocidec1/cvs/Root
ata/rtl/vhdl/ocidec1/cvs/Template
ata/rtl/vhdl/ocidec1/cvs
ata/rtl/vhdl/ocidec1/revision_history.txt
ata/rtl/vhdl/ocidec1/ro_cnt.vhd
ata/rtl/vhdl/ocidec1/ud_cnt.vhd
ata/rtl/vhdl/ocidec1
ata/rtl/vhdl/ocidec2/atahost_controller.vhd
ata/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd
ata/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec2/atahost_top.vhd
ata/rtl/vhdl/ocidec2/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec2/cvs/Entries
ata/rtl/vhdl/ocidec2/cvs/Repository
ata/rtl/vhdl/ocidec2/cvs/Root
ata/rtl/vhdl/ocidec2/cvs/Template
ata/rtl/vhdl/ocidec2/cvs
ata/rtl/vhdl/ocidec2/revision_history.txt
ata/rtl/vhdl/ocidec2/ro_cnt.vhd
ata/rtl/vhdl/ocidec2/ud_cnt.vhd
ata/rtl/vhdl/ocidec2
ata/rtl/vhdl/ocidec3/atahost_controller.vhd
ata/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd
ata/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd
ata/rtl/vhdl/ocidec3/atahost_fifo.vhd
ata/rtl/vhdl/ocidec3/atahost_lfsr.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_controller.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec3/atahost_reg_buf.vhd
ata/rtl/vhdl/ocidec3/atahost_top.vhd
ata/rtl/vhdl/ocidec3/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec3/cvs/Entries
ata/rtl/vhdl/ocidec3/cvs/Repository
ata/rtl/vhdl/ocidec3/cvs/Root
ata/rtl/vhdl/ocidec3/cvs/Template
ata/rtl/vhdl/ocidec3/cvs
ata/rtl/vhdl/ocidec3/revision_history.txt
ata/rtl/vhdl/ocidec3/ro_cnt.vhd
ata/rtl/vhdl/ocidec3/ud_cnt.vhd
ata/rtl/vhdl/ocidec3
ata/rtl/vhdl
ata/rtl
ata/sim/cvs/Entries
ata/sim/cvs/Repository
ata/sim/cvs/Root
ata/sim/cvs/Template
ata/sim/cvs
ata/sim/rtl_sim/bin/cvs/Entries
ata/sim/rtl_sim/bin/cvs/Repository
ata/sim/rtl_sim/bin/cvs/Root
ata/sim/rtl_sim/bin/cvs/Template
ata/sim/rtl_sim/bin/cvs
ata/sim/rtl_sim/bin/Makefile
ata/sim/rtl_sim/bin
ata/sim/rtl_sim/cvs/Entries
ata/sim/rtl_sim/cvs/Repository
ata/sim/rtl_sim/cvs/Root
ata/sim/rtl_sim/cvs/Template
ata/sim/rtl_sim/cvs
ata/sim/rtl_sim
ata/sim
ata/syn/bin/comp.dc
ata/syn/bin/cvs/Entries
ata/syn/bin/cvs/Repository
ata/syn/bin/cvs/Root
ata/syn/bin/cvs/Template
ata/syn/bin/cvs
ata/syn/bin/design_spec.dc
ata/syn/bin/lib_spec.dc
ata/syn/bin/read.dc
ata/syn/bin
ata/syn/cvs/Entries
ata/syn/cvs/Repository
ata/syn/cvs/Root
ata/syn/cvs/Template
ata/syn/cvs
ata/syn
ata
www.dssz.com.txt
ata/bench/cvs/Repository
ata/bench/cvs/Root
ata/bench/cvs/Template
ata/bench/cvs
ata/bench/verilog/ata_device.v
ata/bench/verilog/cvs/Entries
ata/bench/verilog/cvs/Repository
ata/bench/verilog/cvs/Root
ata/bench/verilog/cvs/Template
ata/bench/verilog/cvs
ata/bench/verilog/tests.v
ata/bench/verilog/test_bench_top.v
ata/bench/verilog/wb_mast_model.v
ata/bench/verilog/wb_model_defines.v
ata/bench/verilog/wb_slv_model.v
ata/bench/verilog
ata/bench
ata/cvs/Entries
ata/cvs/Repository
ata/cvs/Root
ata/cvs/Template
ata/cvs
ata/doc/cvs/Entries
ata/doc/cvs/Repository
ata/doc/cvs/Root
ata/doc/cvs/Template
ata/doc/cvs
ata/doc/preliminary_ata_core.pdf
ata/doc/src/ata_core.doc
ata/doc/src/cvs/Entries
ata/doc/src/cvs/Repository
ata/doc/src/cvs/Root
ata/doc/src/cvs/Template
ata/doc/src/cvs
ata/doc/src
ata/doc
ata/rtl/cvs/Entries
ata/rtl/cvs/Repository
ata/rtl/cvs/Root
ata/rtl/cvs/Template
ata/rtl/cvs
ata/rtl/verilog/cvs/Entries
ata/rtl/verilog/cvs/Repository
ata/rtl/verilog/cvs/Root
ata/rtl/verilog/cvs/Template
ata/rtl/verilog/cvs
ata/rtl/verilog/ocidec-1/atahost_controller.v
ata/rtl/verilog/ocidec-1/atahost_pio_tctrl.v
ata/rtl/verilog/ocidec-1/atahost_top.v
ata/rtl/verilog/ocidec-1/atahost_wb_slave.v
ata/rtl/verilog/ocidec-1/cvs/Entries
ata/rtl/verilog/ocidec-1/cvs/Repository
ata/rtl/verilog/ocidec-1/cvs/Root
ata/rtl/verilog/ocidec-1/cvs/Template
ata/rtl/verilog/ocidec-1/cvs
ata/rtl/verilog/ocidec-1/revision_history.txt
ata/rtl/verilog/ocidec-1/ro_cnt.v
ata/rtl/verilog/ocidec-1/timescale.v
ata/rtl/verilog/ocidec-1/ud_cnt.v
ata/rtl/verilog/ocidec-1
ata/rtl/verilog/ocidec-2/atahost_controller.v
ata/rtl/verilog/ocidec-2/atahost_pio_actrl.v
ata/rtl/verilog/ocidec-2/atahost_pio_tctrl.v
ata/rtl/verilog/ocidec-2/atahost_top.v
ata/rtl/verilog/ocidec-2/atahost_wb_slave.v
ata/rtl/verilog/ocidec-2/cvs/Entries
ata/rtl/verilog/ocidec-2/cvs/Repository
ata/rtl/verilog/ocidec-2/cvs/Root
ata/rtl/verilog/ocidec-2/cvs/Template
ata/rtl/verilog/ocidec-2/cvs
ata/rtl/verilog/ocidec-2/revision_history.txt
ata/rtl/verilog/ocidec-2/ro_cnt.v
ata/rtl/verilog/ocidec-2/timescale.v
ata/rtl/verilog/ocidec-2/ud_cnt.v
ata/rtl/verilog/ocidec-2
ata/rtl/verilog
ata/rtl/vhdl/cvs/Entries
ata/rtl/vhdl/cvs/Repository
ata/rtl/vhdl/cvs/Root
ata/rtl/vhdl/cvs/Template
ata/rtl/vhdl/cvs
ata/rtl/vhdl/ocidec1/atahost_controller.vhd
ata/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec1/atahost_top.vhd
ata/rtl/vhdl/ocidec1/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec1/cvs/Entries
ata/rtl/vhdl/ocidec1/cvs/Repository
ata/rtl/vhdl/ocidec1/cvs/Root
ata/rtl/vhdl/ocidec1/cvs/Template
ata/rtl/vhdl/ocidec1/cvs
ata/rtl/vhdl/ocidec1/revision_history.txt
ata/rtl/vhdl/ocidec1/ro_cnt.vhd
ata/rtl/vhdl/ocidec1/ud_cnt.vhd
ata/rtl/vhdl/ocidec1
ata/rtl/vhdl/ocidec2/atahost_controller.vhd
ata/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd
ata/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec2/atahost_top.vhd
ata/rtl/vhdl/ocidec2/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec2/cvs/Entries
ata/rtl/vhdl/ocidec2/cvs/Repository
ata/rtl/vhdl/ocidec2/cvs/Root
ata/rtl/vhdl/ocidec2/cvs/Template
ata/rtl/vhdl/ocidec2/cvs
ata/rtl/vhdl/ocidec2/revision_history.txt
ata/rtl/vhdl/ocidec2/ro_cnt.vhd
ata/rtl/vhdl/ocidec2/ud_cnt.vhd
ata/rtl/vhdl/ocidec2
ata/rtl/vhdl/ocidec3/atahost_controller.vhd
ata/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd
ata/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd
ata/rtl/vhdl/ocidec3/atahost_fifo.vhd
ata/rtl/vhdl/ocidec3/atahost_lfsr.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_controller.vhd
ata/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd
ata/rtl/vhdl/ocidec3/atahost_reg_buf.vhd
ata/rtl/vhdl/ocidec3/atahost_top.vhd
ata/rtl/vhdl/ocidec3/atahost_wb_slave.vhd
ata/rtl/vhdl/ocidec3/cvs/Entries
ata/rtl/vhdl/ocidec3/cvs/Repository
ata/rtl/vhdl/ocidec3/cvs/Root
ata/rtl/vhdl/ocidec3/cvs/Template
ata/rtl/vhdl/ocidec3/cvs
ata/rtl/vhdl/ocidec3/revision_history.txt
ata/rtl/vhdl/ocidec3/ro_cnt.vhd
ata/rtl/vhdl/ocidec3/ud_cnt.vhd
ata/rtl/vhdl/ocidec3
ata/rtl/vhdl
ata/rtl
ata/sim/cvs/Entries
ata/sim/cvs/Repository
ata/sim/cvs/Root
ata/sim/cvs/Template
ata/sim/cvs
ata/sim/rtl_sim/bin/cvs/Entries
ata/sim/rtl_sim/bin/cvs/Repository
ata/sim/rtl_sim/bin/cvs/Root
ata/sim/rtl_sim/bin/cvs/Template
ata/sim/rtl_sim/bin/cvs
ata/sim/rtl_sim/bin/Makefile
ata/sim/rtl_sim/bin
ata/sim/rtl_sim/cvs/Entries
ata/sim/rtl_sim/cvs/Repository
ata/sim/rtl_sim/cvs/Root
ata/sim/rtl_sim/cvs/Template
ata/sim/rtl_sim/cvs
ata/sim/rtl_sim
ata/sim
ata/syn/bin/comp.dc
ata/syn/bin/cvs/Entries
ata/syn/bin/cvs/Repository
ata/syn/bin/cvs/Root
ata/syn/bin/cvs/Template
ata/syn/bin/cvs
ata/syn/bin/design_spec.dc
ata/syn/bin/lib_spec.dc
ata/syn/bin/read.dc
ata/syn/bin
ata/syn/cvs/Entries
ata/syn/cvs/Repository
ata/syn/cvs/Root
ata/syn/cvs/Template
ata/syn/cvs
ata/syn
ata
www.dssz.com.txt
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