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文件名称:Xil3SD1800A_MIG

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.16mb
  • 已下载：
    0次
  • 提 供 者：
    soni*****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
相关搜索： .ucf DDR2 ipcore

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Xil3SD1800A_MIG/datasheet.txt
Xil3SD1800A_MIG/log.txt
Xil3SD1800A_MIG/par/create_ise.bat
Xil3SD1800A_MIG/par/icon_coregen.xco
Xil3SD1800A_MIG/par/ila_coregen.xco
Xil3SD1800A_MIG/par/ise_flow.bat
Xil3SD1800A_MIG/par/ise_run.txt
Xil3SD1800A_MIG/par/mem_interface_top.ut
Xil3SD1800A_MIG/par/MIG_new.ucf
Xil3SD1800A_MIG/par/readme.txt
Xil3SD1800A_MIG/par/set_ise_prop.txt
Xil3SD1800A_MIG/par/vio_coregen.xco
Xil3SD1800A_MIG/rtl/MIG_new.vhd
Xil3SD1800A_MIG/rtl/MIG_new_cal_ctl.vhd
Xil3SD1800A_MIG/rtl/MIG_new_cal_top.vhd
Xil3SD1800A_MIG/rtl/MIG_new_clk_dcm.vhd
Xil3SD1800A_MIG/rtl/MIG_new_controller_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_controller_iobs_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_data_path_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_data_path_iobs_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_data_read_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_data_read_controller_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_data_write_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_dqs_delay_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_fifo_0_wr_en_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_fifo_1_wr_en_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_infrastructure.vhd
Xil3SD1800A_MIG/rtl/MIG_new_infrastructure_iobs_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_infrastructure_top.vhd
Xil3SD1800A_MIG/rtl/MIG_new_iobs_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_parameters_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_ram8d_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_rd_gray_cntr.vhd
Xil3SD1800A_MIG/rtl/MIG_new_s3_dm_iob.vhd
Xil3SD1800A_MIG/rtl/MIG_new_s3_dqs_iob.vhd
Xil3SD1800A_MIG/rtl/MIG_new_s3_dq_iob.vhd
Xil3SD1800A_MIG/rtl/MIG_new_tap_dly.vhd
Xil3SD1800A_MIG/rtl/MIG_new_top_0.vhd
Xil3SD1800A_MIG/rtl/MIG_new_wr_gray_cntr.vhd
Xil3SD1800A_MIG/sim/ddr2_model.v
Xil3SD1800A_MIG/sim/ddr2_model.v.bak
Xil3SD1800A_MIG/sim/ddr2_model_parameters.vh
Xil3SD1800A_MIG/sim/glbl.v
Xil3SD1800A_MIG/sim/MIG_new_addr_gen_0.vhd
Xil3SD1800A_MIG/sim/MIG_new_cmd_fsm_0.vhd
Xil3SD1800A_MIG/sim/MIG_new_cmp_data_0.vhd
Xil3SD1800A_MIG/sim/MIG_new_data_gen_0.vhd
Xil3SD1800A_MIG/sim/MIG_new_test_bench_0.vhd
Xil3SD1800A_MIG/sim/sim.do
Xil3SD1800A_MIG/sim/sim.exe
Xil3SD1800A_MIG/sim/simulation_help.chm
Xil3SD1800A_MIG/sim/sim_log.txt
Xil3SD1800A_MIG/sim/sim_tb_top.vhd
Xil3SD1800A_MIG/sim/transcript
Xil3SD1800A_MIG/sim/wiredly.vhd
Xil3SD1800A_MIG/sim/work/ddr2_model/verilog.asm
Xil3SD1800A_MIG/sim/work/ddr2_model/verilog.rw
Xil3SD1800A_MIG/sim/work/ddr2_model/_primary.dat
Xil3SD1800A_MIG/sim/work/ddr2_model/_primary.dbs
Xil3SD1800A_MIG/sim/work/ddr2_model/_primary.vhd
Xil3SD1800A_MIG/sim/work/glbl/verilog.asm
Xil3SD1800A_MIG/sim/work/glbl/verilog.rw
Xil3SD1800A_MIG/sim/work/glbl/_primary.dat
Xil3SD1800A_MIG/sim/work/glbl/_primary.dbs
Xil3SD1800A_MIG/sim/work/glbl/_primary.vhd
Xil3SD1800A_MIG/sim/work/mig_new/arc_mem_interface_top.asm
Xil3SD1800A_MIG/sim/work/mig_new/arc_mem_interface_top.dat
Xil3SD1800A_MIG/sim/work/mig_new/arc_mem_interface_top.dbs
Xil3SD1800A_MIG/sim/work/mig_new/arc_mem_interface_top.rw
Xil3SD1800A_MIG/sim/work/mig_new/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_addr_gen_0/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/arc_cal_ctl.asm
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/arc_cal_ctl.dat
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/arc_cal_ctl.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/arc_cal_ctl.rw
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_cal_ctl/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_cal_top/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_clk_dcm/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_cmd_fsm_0/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/_primary.dat
Xil3SD1800A_MIG/sim/work/mig_new_cmp_data_0/_primary.dbs
Xil3SD1800A_MIG/sim/work/mig_new_controller_0/arc.asm
Xil3SD1800A_MIG/sim/work/mig_new_controller_0/arc.dat
Xil3SD1800A_MIG/sim/work/mig_new_controller_0/arc.dbs
Xil3SD1800A_MIG/sim/work/mig_new_controller_0/arc.rw
Xil3SD1800A_MIG/sim/work/mig_new_controller_0/

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