文件名称:RD1008
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- 上传时间:2012-11-16
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文件大小:716.17kb
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Receiver module design i am uploding it thax
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下载文件列表
RD1008/Docs/rd1008.pdf
RD1008/Docs/RD1008_readme.txt
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.lci
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.lct
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.sty
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.syn
RD1008/Project/MACH4A3/verilog/pci_tb_tfa.udo
RD1008/Project/MACH4A3/verilog/pci_tb_tffa.udo
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.lci
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.lct
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.sty
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.syn
RD1008/Project/MACH4A3/vhdl/pci_tb_vhda.udo
RD1008/Project/MACH4A3/vhdl/pci_tb_vhdaf.udo
RD1008/Project/xo/verilog/pci_target_33mhz_verilog.lpf
RD1008/Project/xo/verilog/pci_target_33MHz_verilog.syn
RD1008/Project/xo/verilog/pci_tb_tf.udo
RD1008/Project/xo/verilog/pci_tb_tff.udo
RD1008/Project/xo/verilog/pci_tb_tfr.udo
RD1008/Project/xo/vhdl/pci_target_33mhz_vhdl.lpf
RD1008/Project/xo/vhdl/pci_target_33mhz_vhdl.syn
RD1008/Project/xo/vhdl/pci_tb_vhd.udo
RD1008/Project/xo/vhdl/pci_tb_vhdf.udo
RD1008/Project/xo/vhdl/pci_tb_vhdr.udo
RD1008/Project/xp2/verilog/pci_target_33mhz_verilog.lpf
RD1008/Project/xp2/verilog/pci_target_33mhz_verilog.syn
RD1008/Project/xp2/verilog/pci_tb_tf.udo
RD1008/Project/xp2/verilog/pci_tb_tff.udo
RD1008/Project/xp2/verilog/pci_tb_tfr.udo
RD1008/Project/xp2/vhdl/pci_target_33mhz_vhdl.lpf
RD1008/Project/xp2/vhdl/pci_target_33mhz_vhdl.syn
RD1008/Project/xp2/vhdl/pci_tb_vhd.udo
RD1008/Project/xp2/vhdl/pci_tb_vhdf.udo
RD1008/Project/xp2/vhdl/pci_tb_vhdr.udo
RD1008/Source/verilog/base_addr_chk.v
RD1008/Source/verilog/config_mux.v
RD1008/Source/verilog/glue.v
RD1008/Source/verilog/pargen.v
RD1008/Source/verilog/pci_top.v
RD1008/Source/verilog/retry_count.v
RD1008/Source/verilog/state_machine.v
RD1008/Source/vhdl/base_addr_chk.vhd
RD1008/Source/vhdl/config_mux.vhd
RD1008/Source/vhdl/glue.vhd
RD1008/Source/vhdl/pargen.vhd
RD1008/Source/vhdl/pci_top.vhd
RD1008/Source/vhdl/retry_count.vhd
RD1008/Source/vhdl/state_machine.vhd
RD1008/Testbench/verilog/bkend_daemon.v
RD1008/Testbench/verilog/pci_clk_reset.v
RD1008/Testbench/verilog/pci_stim.v
RD1008/Testbench/verilog/pci_tb.v
RD1008/Testbench/verilog/tasks.v
RD1008/Testbench/verilog_for_classic/pci_tb.v
RD1008/Testbench/vhdl/bkend_daemon.vhd
RD1008/Testbench/vhdl/lattice_lib.vhd
RD1008/Testbench/vhdl/pci_clk_reset.vhd
RD1008/Testbench/vhdl/pci_stim.vhd
RD1008/Testbench/vhdl/pci_tb.vhd
RD1008/Testbench/vhdl_for_classic/pci_tb.vhd
RD1008/Project/MACH4A3/verilog
RD1008/Project/MACH4A3/vhdl
RD1008/Project/xo/verilog
RD1008/Project/xo/vhdl
RD1008/Project/xp2/verilog
RD1008/Project/xp2/vhdl
RD1008/Project/MACH4A3
RD1008/Project/xo
RD1008/Project/xp2
RD1008/Source/verilog
RD1008/Source/vhdl
RD1008/Testbench/verilog
RD1008/Testbench/verilog_for_classic
RD1008/Testbench/vhdl
RD1008/Testbench/vhdl_for_classic
RD1008/Docs
RD1008/Project
RD1008/Source
RD1008/Testbench
RD1008
RD1008/Docs/RD1008_readme.txt
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.lci
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.lct
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.sty
RD1008/Project/MACH4A3/verilog/pci_target_33mhz_verilog_mach4a3.syn
RD1008/Project/MACH4A3/verilog/pci_tb_tfa.udo
RD1008/Project/MACH4A3/verilog/pci_tb_tffa.udo
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.lci
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.lct
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.sty
RD1008/Project/MACH4A3/vhdl/pci_target_33mhz_vhdl_mach4a3.syn
RD1008/Project/MACH4A3/vhdl/pci_tb_vhda.udo
RD1008/Project/MACH4A3/vhdl/pci_tb_vhdaf.udo
RD1008/Project/xo/verilog/pci_target_33mhz_verilog.lpf
RD1008/Project/xo/verilog/pci_target_33MHz_verilog.syn
RD1008/Project/xo/verilog/pci_tb_tf.udo
RD1008/Project/xo/verilog/pci_tb_tff.udo
RD1008/Project/xo/verilog/pci_tb_tfr.udo
RD1008/Project/xo/vhdl/pci_target_33mhz_vhdl.lpf
RD1008/Project/xo/vhdl/pci_target_33mhz_vhdl.syn
RD1008/Project/xo/vhdl/pci_tb_vhd.udo
RD1008/Project/xo/vhdl/pci_tb_vhdf.udo
RD1008/Project/xo/vhdl/pci_tb_vhdr.udo
RD1008/Project/xp2/verilog/pci_target_33mhz_verilog.lpf
RD1008/Project/xp2/verilog/pci_target_33mhz_verilog.syn
RD1008/Project/xp2/verilog/pci_tb_tf.udo
RD1008/Project/xp2/verilog/pci_tb_tff.udo
RD1008/Project/xp2/verilog/pci_tb_tfr.udo
RD1008/Project/xp2/vhdl/pci_target_33mhz_vhdl.lpf
RD1008/Project/xp2/vhdl/pci_target_33mhz_vhdl.syn
RD1008/Project/xp2/vhdl/pci_tb_vhd.udo
RD1008/Project/xp2/vhdl/pci_tb_vhdf.udo
RD1008/Project/xp2/vhdl/pci_tb_vhdr.udo
RD1008/Source/verilog/base_addr_chk.v
RD1008/Source/verilog/config_mux.v
RD1008/Source/verilog/glue.v
RD1008/Source/verilog/pargen.v
RD1008/Source/verilog/pci_top.v
RD1008/Source/verilog/retry_count.v
RD1008/Source/verilog/state_machine.v
RD1008/Source/vhdl/base_addr_chk.vhd
RD1008/Source/vhdl/config_mux.vhd
RD1008/Source/vhdl/glue.vhd
RD1008/Source/vhdl/pargen.vhd
RD1008/Source/vhdl/pci_top.vhd
RD1008/Source/vhdl/retry_count.vhd
RD1008/Source/vhdl/state_machine.vhd
RD1008/Testbench/verilog/bkend_daemon.v
RD1008/Testbench/verilog/pci_clk_reset.v
RD1008/Testbench/verilog/pci_stim.v
RD1008/Testbench/verilog/pci_tb.v
RD1008/Testbench/verilog/tasks.v
RD1008/Testbench/verilog_for_classic/pci_tb.v
RD1008/Testbench/vhdl/bkend_daemon.vhd
RD1008/Testbench/vhdl/lattice_lib.vhd
RD1008/Testbench/vhdl/pci_clk_reset.vhd
RD1008/Testbench/vhdl/pci_stim.vhd
RD1008/Testbench/vhdl/pci_tb.vhd
RD1008/Testbench/vhdl_for_classic/pci_tb.vhd
RD1008/Project/MACH4A3/verilog
RD1008/Project/MACH4A3/vhdl
RD1008/Project/xo/verilog
RD1008/Project/xo/vhdl
RD1008/Project/xp2/verilog
RD1008/Project/xp2/vhdl
RD1008/Project/MACH4A3
RD1008/Project/xo
RD1008/Project/xp2
RD1008/Source/verilog
RD1008/Source/vhdl
RD1008/Testbench/verilog
RD1008/Testbench/verilog_for_classic
RD1008/Testbench/vhdl
RD1008/Testbench/vhdl_for_classic
RD1008/Docs
RD1008/Project
RD1008/Source
RD1008/Testbench
RD1008
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