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文件名称:ADD6
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- 上传时间:2012-11-16
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文件大小:3.77kb
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此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to achieve the 4 S 2 MUX, a variety of ways to achieve a half adder, a variety of ways to achieve a full adder, ways to achieve the 4-bit full adder, the output of a variety of ways to achieve UDP component, two clock signals, the selector and a variety of simulation source code.
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ADD6.txt
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