Improve design efficiency and reduce costs with this practical guide to formal and

simulation-based functional verification. Giving you a theoretical and practical

understanding of the key issues involved, expert authors explain both formal

techniques (model checking and equivalence checking) and simulation-based

techniques (coverage metrics and test generation). You get insights into practical

issues including hardware verification languages (HVLs) and system-level debugging.

The foundations of formal and simulation-based techniques are covered too, as are

more recent research advances including transaction-level modeling and assertionbased

verification, plus the theoretical underpinnings of verification, including the use

of decision diagrams and Boolean satisfiability (SAT).