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文件名称:FPGA_SDRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.33mb
  • 已下载：
    0次
  • 提 供 者：
    MR***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这个工程主要使用FPGA来对SRAM简单快速的操作，使用的是IS62LV256-70U芯片，文件中含有该芯片的datasheet-The project is mainly used for SRAM FPGA to a quick and easy operation, use the chips IS62LV256-70U, the file containing the chip' s datasheet
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA_SDRAM/datasheet/042174sdr_product_guide_nov_07.pdf
FPGA_SDRAM/datasheet/044975sdr_device_operation_jul_06.pdf
FPGA_SDRAM/datasheet/299156SDRAM_code.pdf
FPGA_SDRAM/datasheet/678733sdr_timing_diagram_feb_04.pdf
FPGA_SDRAM/datasheet/ds_k4s64xx32k_rev11.pdf
FPGA_SDRAM/datasheet/reference_verilog/README.v
FPGA_SDRAM/datasheet/reference_verilog/SDRSD50_071010.v
FPGA_SDRAM/sdram_mdl/datagene.v
FPGA_SDRAM/sdram_mdl/db/add_sub_918.tdf
FPGA_SDRAM/sdram_mdl/db/add_sub_gub.tdf
FPGA_SDRAM/sdram_mdl/db/add_sub_se8.tdf
FPGA_SDRAM/sdram_mdl/db/altsyncram_1lh1.tdf
FPGA_SDRAM/sdram_mdl/db/alt_synch_pipe_oc8.tdf
FPGA_SDRAM/sdram_mdl/db/alt_synch_pipe_pc8.tdf
FPGA_SDRAM/sdram_mdl/db/alt_sync_fifo_0fm.tdf
FPGA_SDRAM/sdram_mdl/db/alt_sync_fifo_0oi.tdf
FPGA_SDRAM/sdram_mdl/db/a_fefifo_ctc.tdf
FPGA_SDRAM/sdram_mdl/db/a_fefifo_htc.tdf
FPGA_SDRAM/sdram_mdl/db/a_gray2bin_q4b.tdf
FPGA_SDRAM/sdram_mdl/db/a_graycounter_u06.tdf
FPGA_SDRAM/sdram_mdl/db/cntr_cta.tdf
FPGA_SDRAM/sdram_mdl/db/cntr_kua.tdf
FPGA_SDRAM/sdram_mdl/db/dcfifo_35l1.tdf
FPGA_SDRAM/sdram_mdl/db/dcfifo_o2l1.tdf
FPGA_SDRAM/sdram_mdl/db/dffpipe_gd9.tdf
FPGA_SDRAM/sdram_mdl/db/dffpipe_id9.tdf
FPGA_SDRAM/sdram_mdl/db/dffpipe_jd9.tdf
FPGA_SDRAM/sdram_mdl/db/dpram_6o31.tdf
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.asm.qmsg
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.eda.qmsg
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.fit.qmsg
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.map.qmsg
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.qmsg
FPGA_SDRAM/sdram_mdl/db/prev_cmp_sdr_test.sta.qmsg
FPGA_SDRAM/sdram_mdl/db/sdr_test.db_info
FPGA_SDRAM/sdram_mdl/db/sdr_test.eco.cdb
FPGA_SDRAM/sdram_mdl/db/sdr_test.sld_design_entry.sci
FPGA_SDRAM/sdram_mdl/db/sdr_test_global_asgn_op.abo
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.atm
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.cdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.dfp
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.hdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.hdbx
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.kpt
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.logdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.rcf
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.cmp.rcfdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.atm
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.cdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.dpi
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.hdb
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.hdbx
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.map.kpt
FPGA_SDRAM/sdram_mdl/incremental_db/compiled_partitions/sdr_test.root_partition.merge_hb.atm
FPGA_SDRAM/sdram_mdl/incremental_db/README
FPGA_SDRAM/sdram_mdl/init_state_r.jpg
FPGA_SDRAM/sdram_mdl/PLL_ctrl.bsf
FPGA_SDRAM/sdram_mdl/PLL_ctrl.ppf
FPGA_SDRAM/sdram_mdl/PLL_ctrl.qip
FPGA_SDRAM/sdram_mdl/PLL_ctrl.v
FPGA_SDRAM/sdram_mdl/PLL_ctrl_bb.v
FPGA_SDRAM/sdram_mdl/PLL_ctrl_inst.v
FPGA_SDRAM/sdram_mdl/PLL_ctrl_wave0.jpg
FPGA_SDRAM/sdram_mdl/PLL_ctrl_waveforms.html
FPGA_SDRAM/sdram_mdl/rdfifo.bsf
FPGA_SDRAM/sdram_mdl/rdfifo.qip
FPGA_SDRAM/sdram_mdl/rdfifo.v
FPGA_SDRAM/sdram_mdl/rdfifo_bb.v
FPGA_SDRAM/sdram_mdl/rdfifo_inst.v
FPGA_SDRAM/sdram_mdl/rdfifo_wave0.jpg
FPGA_SDRAM/sdram_mdl/rdfifo_waveforms.html
FPGA_SDRAM/sdram_mdl/sdfifo_ctrl.v
FPGA_SDRAM/sdram_mdl/sdfifo_ctrl_uut_sdffifoctrl.jpg
FPGA_SDRAM/sdram_mdl/sdram_cmd.v
FPGA_SDRAM/sdram_mdl/sdram_ctrl.v
FPGA_SDRAM/sdram_mdl/sdram_top.v
FPGA_SDRAM/sdram_mdl/sdram_top_uut_sdramtop.jpg
FPGA_SDRAM/sdram_mdl/sdram_wr_data.v
FPGA_SDRAM/sdram_mdl/sdr_para.v
FPGA_SDRAM/sdram_mdl/sdr_test.asm.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.cdf
FPGA_SDRAM/sdram_mdl/sdr_test.done
FPGA_SDRAM/sdram_mdl/sdr_test.dpf
FPGA_SDRAM/sdram_mdl/sdr_test.eda.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.fit.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.fit.smsg
FPGA_SDRAM/sdram_mdl/sdr_test.fit.summary
FPGA_SDRAM/sdram_mdl/sdr_test.flow.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.jpg
FPGA_SDRAM/sdram_mdl/sdr_test.map.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.map.summary
FPGA_SDRAM/sdram_mdl/sdr_test.pin
FPGA_SDRAM/sdram_mdl/sdr_test.pof
FPGA_SDRAM/sdram_mdl/sdr_test.qpf
FPGA_SDRAM/sdram_mdl/sdr_test.qsf
FPGA_SDRAM/sdram_mdl/sdr_test.qws
FPGA_SDRAM/sdram_mdl/sdr_test.rar
FPGA_SDRAM/sdram_mdl/sdr_test.sdc
FPGA_SDRAM/sdram_mdl/sdr_test.sof
FPGA_SDRAM/sdram_mdl/sdr_test.sta.rpt
FPGA_SDRAM/sdram_mdl/sdr_test.sta.summary
FPGA_SDRAM/sdram_mdl/sdr_test.v
FPGA_SDRAM/sdram_mdl/sdr_test_assignment_defaults.qdf
FPGA_SDRAM/sdram_mdl/simulation/modelsim/altera_mf.v
FPGA_SDRAM/sdram_mdl/simulation/modelsim/cyclone_atoms.v
FPGA_SDRAM/sdram_mdl/simulation/modelsim/print_task.v
FPGA_SDRA

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