文件名称:VGA_char
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- 上传时间:2012-11-16
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文件大小:428.75kb
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已下载:0次
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Verilog语言描述的VGA显示实验,主要目的是在屏幕上显示不同的字符,Quartus 10 中编译通过。-Verilog language descr iption of the VGA display experiment, the main purpose is to display different characters on the screen, Quartus 10 in the compile.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA_char/
VGA_char/VGA_char.asm.rpt
VGA_char/VGA_char.cdf
VGA_char/VGA_char.done
VGA_char/VGA_char.dpf
VGA_char/VGA_char.eda.rpt
VGA_char/VGA_char.fit.rpt
VGA_char/VGA_char.fit.smsg
VGA_char/VGA_char.fit.summary
VGA_char/VGA_char.flow.rpt
VGA_char/VGA_char.map.rpt
VGA_char/VGA_char.map.summary
VGA_char/VGA_char.pin
VGA_char/VGA_char.pof
VGA_char/VGA_char.qpf
VGA_char/VGA_char.qsf
VGA_char/VGA_char.qws
VGA_char/VGA_char.sof
VGA_char/VGA_char.tan.rpt
VGA_char/VGA_char.tan.summary
VGA_char/VGA_char.v
VGA_char/VGA_char.v.bak
VGA_char/VGA_char_nativelink_simulation.rpt
VGA_char/db/
VGA_char/db/VGA_char.(0).cnf.cdb
VGA_char/db/VGA_char.(0).cnf.hdb
VGA_char/db/VGA_char.asm.qmsg
VGA_char/db/VGA_char.asm.rdb
VGA_char/db/VGA_char.cbx.xml
VGA_char/db/VGA_char.cmp.bpm
VGA_char/db/VGA_char.cmp.cdb
VGA_char/db/VGA_char.cmp.ecobp
VGA_char/db/VGA_char.cmp.hdb
VGA_char/db/VGA_char.cmp.kpt
VGA_char/db/VGA_char.cmp.logdb
VGA_char/db/VGA_char.cmp.rdb
VGA_char/db/VGA_char.cmp.tdb
VGA_char/db/VGA_char.cmp0.ddb
VGA_char/db/VGA_char.cmp_merge.kpt
VGA_char/db/VGA_char.db_info
VGA_char/db/VGA_char.eco.cdb
VGA_char/db/VGA_char.eda.qmsg
VGA_char/db/VGA_char.fit.qmsg
VGA_char/db/VGA_char.hier_info
VGA_char/db/VGA_char.hif
VGA_char/db/VGA_char.lpc.html
VGA_char/db/VGA_char.lpc.rdb
VGA_char/db/VGA_char.lpc.txt
VGA_char/db/VGA_char.map.bpm
VGA_char/db/VGA_char.map.cdb
VGA_char/db/VGA_char.map.ecobp
VGA_char/db/VGA_char.map.hdb
VGA_char/db/VGA_char.map.kpt
VGA_char/db/VGA_char.map.logdb
VGA_char/db/VGA_char.map.qmsg
VGA_char/db/VGA_char.map_bb.cdb
VGA_char/db/VGA_char.map_bb.hdb
VGA_char/db/VGA_char.map_bb.logdb
VGA_char/db/VGA_char.pre_map.cdb
VGA_char/db/VGA_char.pre_map.hdb
VGA_char/db/VGA_char.rtlv.hdb
VGA_char/db/VGA_char.rtlv_sg.cdb
VGA_char/db/VGA_char.rtlv_sg_swap.cdb
VGA_char/db/VGA_char.sgdiff.cdb
VGA_char/db/VGA_char.sgdiff.hdb
VGA_char/db/VGA_char.sld_design_entry.sci
VGA_char/db/VGA_char.sld_design_entry_dsc.sci
VGA_char/db/VGA_char.smart_action.txt
VGA_char/db/VGA_char.syn_hier_info
VGA_char/db/VGA_char.tan.qmsg
VGA_char/db/VGA_char.tis_db_list.ddb
VGA_char/db/VGA_char.tmw_info
VGA_char/db/logic_util_heursitic.dat
VGA_char/db/prev_cmp_VGA_char.eda.qmsg
VGA_char/db/prev_cmp_VGA_char.map.qmsg
VGA_char/db/prev_cmp_VGA_char.qmsg
VGA_char/incremental_db/
VGA_char/incremental_db/README
VGA_char/incremental_db/compiled_partitions/
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.cdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.dfp
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.hdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.kpt
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.logdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.rcfdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.re.rcfdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.cdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.dpi
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.hdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.kpt
VGA_char/output_file.jic
VGA_char/output_file.map
VGA_char/simulation/
VGA_char/simulation/modelsim/
VGA_char/simulation/modelsim/VGA_char.sft
VGA_char/simulation/modelsim/VGA_char.vo
VGA_char/simulation/modelsim/VGA_char.vt
VGA_char/simulation/modelsim/VGA_char.vt.bak
VGA_char/simulation/modelsim/VGA_char_modelsim.xrf
VGA_char/simulation/modelsim/VGA_char_run_msim_rtl_verilog.do
VGA_char/simulation/modelsim/VGA_char_v.sdo
VGA_char/simulation/modelsim/modelsim.ini
VGA_char/simulation/modelsim/msim_transcript
VGA_char/simulation/modelsim/rtl_work/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.dat
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.dbs
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.vhd
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/verilog.prw
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/verilog.psm
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.dat
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.dbs
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.vhd
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/verilog.prw
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/verilog.psm
VGA_char/simulation/modelsim/rtl_work/_info
VGA_char/simulation/modelsim/rtl_work/_temp/
VGA_char/simulation/modelsim/rtl_work/_vmake
VGA_char/vga_char.jic
VGA_char/vga_char.map
VGA_char/VGA_char.asm.rpt
VGA_char/VGA_char.cdf
VGA_char/VGA_char.done
VGA_char/VGA_char.dpf
VGA_char/VGA_char.eda.rpt
VGA_char/VGA_char.fit.rpt
VGA_char/VGA_char.fit.smsg
VGA_char/VGA_char.fit.summary
VGA_char/VGA_char.flow.rpt
VGA_char/VGA_char.map.rpt
VGA_char/VGA_char.map.summary
VGA_char/VGA_char.pin
VGA_char/VGA_char.pof
VGA_char/VGA_char.qpf
VGA_char/VGA_char.qsf
VGA_char/VGA_char.qws
VGA_char/VGA_char.sof
VGA_char/VGA_char.tan.rpt
VGA_char/VGA_char.tan.summary
VGA_char/VGA_char.v
VGA_char/VGA_char.v.bak
VGA_char/VGA_char_nativelink_simulation.rpt
VGA_char/db/
VGA_char/db/VGA_char.(0).cnf.cdb
VGA_char/db/VGA_char.(0).cnf.hdb
VGA_char/db/VGA_char.asm.qmsg
VGA_char/db/VGA_char.asm.rdb
VGA_char/db/VGA_char.cbx.xml
VGA_char/db/VGA_char.cmp.bpm
VGA_char/db/VGA_char.cmp.cdb
VGA_char/db/VGA_char.cmp.ecobp
VGA_char/db/VGA_char.cmp.hdb
VGA_char/db/VGA_char.cmp.kpt
VGA_char/db/VGA_char.cmp.logdb
VGA_char/db/VGA_char.cmp.rdb
VGA_char/db/VGA_char.cmp.tdb
VGA_char/db/VGA_char.cmp0.ddb
VGA_char/db/VGA_char.cmp_merge.kpt
VGA_char/db/VGA_char.db_info
VGA_char/db/VGA_char.eco.cdb
VGA_char/db/VGA_char.eda.qmsg
VGA_char/db/VGA_char.fit.qmsg
VGA_char/db/VGA_char.hier_info
VGA_char/db/VGA_char.hif
VGA_char/db/VGA_char.lpc.html
VGA_char/db/VGA_char.lpc.rdb
VGA_char/db/VGA_char.lpc.txt
VGA_char/db/VGA_char.map.bpm
VGA_char/db/VGA_char.map.cdb
VGA_char/db/VGA_char.map.ecobp
VGA_char/db/VGA_char.map.hdb
VGA_char/db/VGA_char.map.kpt
VGA_char/db/VGA_char.map.logdb
VGA_char/db/VGA_char.map.qmsg
VGA_char/db/VGA_char.map_bb.cdb
VGA_char/db/VGA_char.map_bb.hdb
VGA_char/db/VGA_char.map_bb.logdb
VGA_char/db/VGA_char.pre_map.cdb
VGA_char/db/VGA_char.pre_map.hdb
VGA_char/db/VGA_char.rtlv.hdb
VGA_char/db/VGA_char.rtlv_sg.cdb
VGA_char/db/VGA_char.rtlv_sg_swap.cdb
VGA_char/db/VGA_char.sgdiff.cdb
VGA_char/db/VGA_char.sgdiff.hdb
VGA_char/db/VGA_char.sld_design_entry.sci
VGA_char/db/VGA_char.sld_design_entry_dsc.sci
VGA_char/db/VGA_char.smart_action.txt
VGA_char/db/VGA_char.syn_hier_info
VGA_char/db/VGA_char.tan.qmsg
VGA_char/db/VGA_char.tis_db_list.ddb
VGA_char/db/VGA_char.tmw_info
VGA_char/db/logic_util_heursitic.dat
VGA_char/db/prev_cmp_VGA_char.eda.qmsg
VGA_char/db/prev_cmp_VGA_char.map.qmsg
VGA_char/db/prev_cmp_VGA_char.qmsg
VGA_char/incremental_db/
VGA_char/incremental_db/README
VGA_char/incremental_db/compiled_partitions/
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.cdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.dfp
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.hdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.kpt
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.logdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.rcfdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.cmp.re.rcfdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.cdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.dpi
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.hdb
VGA_char/incremental_db/compiled_partitions/VGA_char.root_partition.map.kpt
VGA_char/output_file.jic
VGA_char/output_file.map
VGA_char/simulation/
VGA_char/simulation/modelsim/
VGA_char/simulation/modelsim/VGA_char.sft
VGA_char/simulation/modelsim/VGA_char.vo
VGA_char/simulation/modelsim/VGA_char.vt
VGA_char/simulation/modelsim/VGA_char.vt.bak
VGA_char/simulation/modelsim/VGA_char_modelsim.xrf
VGA_char/simulation/modelsim/VGA_char_run_msim_rtl_verilog.do
VGA_char/simulation/modelsim/VGA_char_v.sdo
VGA_char/simulation/modelsim/modelsim.ini
VGA_char/simulation/modelsim/msim_transcript
VGA_char/simulation/modelsim/rtl_work/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.dat
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.dbs
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/_primary.vhd
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/verilog.prw
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char/verilog.psm
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.dat
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.dbs
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/_primary.vhd
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/verilog.prw
VGA_char/simulation/modelsim/rtl_work/@v@g@a_char_vlg_tst/verilog.psm
VGA_char/simulation/modelsim/rtl_work/_info
VGA_char/simulation/modelsim/rtl_work/_temp/
VGA_char/simulation/modelsim/rtl_work/_vmake
VGA_char/vga_char.jic
VGA_char/vga_char.map
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