文件名称:reset
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- 上传时间:2012-11-16
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文件大小:371.49kb
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verilog hdl 如何实现软件复位功能-how to get the function of reset with verilog hdl
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clr/smartgen/smartgen.aws
clr/hdl/clr.vhd
clr/viewdraw/vf/project.lst
clr/viewdraw/viewdraw.ini
clr/simulation/run.do
clr/simulation/modelsim.log
clr/simulation/postsynth/_info
clr/simulation/postsynth/_vmake
clr/simulation/postsynth/sys_init/_primary.dbs
clr/simulation/postsynth/sys_init/_primary.dat
clr/simulation/postsynth/sys_init/def_arch.dbs
clr/simulation/postsynth/sys_init/def_arch.dat
clr/simulation/postsynth/sys_init/def_arch.psm
clr/simulation/postsynth/sys_init/def_arch.prw
clr/simulation/postsynth/stimulus/stimulator.psm
clr/simulation/postsynth/stimulus/stimulator.prw
clr/simulation/postsynth/stimulus/_primary.dbs
clr/simulation/postsynth/stimulus/_primary.dat
clr/simulation/postsynth/stimulus/stimulator.dbs
clr/simulation/postsynth/stimulus/stimulator.dat
clr/simulation/postsynth/testbench/tbgeneratedcode.psm
clr/simulation/postsynth/testbench/tbgeneratedcode.prw
clr/simulation/postsynth/testbench/_primary.dbs
clr/simulation/postsynth/testbench/_primary.dat
clr/simulation/postsynth/testbench/tbgeneratedcode.dbs
clr/simulation/postsynth/testbench/tbgeneratedcode.dat
clr/simulation/postsynth/clr/def_arch.psm
clr/simulation/postsynth/clr/def_arch.prw
clr/simulation/postsynth/clr/_primary.dbs
clr/simulation/postsynth/clr/_primary.dat
clr/simulation/postsynth/clr/def_arch.dbs
clr/simulation/postsynth/clr/def_arch.dat
clr/simulation/tb.log
clr/simulation/vsim.wlf
clr/simulation/modelsim.ini.sav
clr/simulation/modelsim.ini
clr/simulation/wave.do
clr/synthesis/stdout.log
clr/synthesis/syntmp/sys_init_flink.htm
clr/synthesis/syntmp/sys_init_srr.htm
clr/synthesis/syntmp/sys_init_toc.htm
clr/synthesis/syntmp/sap.log
clr/synthesis/syntmp/sys_init.plg
clr/synthesis/syntmp/sap_log_flink.htm
clr/synthesis/syntmp/sap_log_srr.htm
clr/synthesis/syntmp/sys_init.msg
clr/synthesis/syntmp/clr_flink.htm
clr/synthesis/syntmp/clr_srr.htm
clr/synthesis/syntmp/clr_toc.htm
clr/synthesis/syntmp/clr.plg
clr/synthesis/syntmp/clr.msg
clr/synthesis/backup/sys_init.srr
clr/synthesis/backup/clr.srr
clr/synthesis/run_options.txt
clr/synthesis/scratchproject.prs
clr/synthesis/sys_init.so
clr/synthesis/sys_init.htm
clr/synthesis/sys_init.tlg
clr/synthesis/.recordref
clr/synthesis/sys_init.srl
clr/synthesis/sys_init.sap
clr/synthesis/sys_init.fse
clr/synthesis/sys_init.szr
clr/synthesis/sys_init.srd
clr/synthesis/sys_init.srm
clr/synthesis/sys_init.map
clr/synthesis/sys_init.edn
clr/synthesis/sys_init.sdf
clr/synthesis/sys_init.pdc
clr/synthesis/sys_init_sdc.sdc
clr/synthesis/sys_init.areasrr
clr/synthesis/sys_init.vhd
clr/synthesis/sys_init_syn.prj
clr/synthesis/sys_init.srr
clr/synthesis/sys_init.srs
clr/synthesis/clr.tlg
clr/synthesis/clr.srl
clr/synthesis/clr.htm
clr/synthesis/clr.sap
clr/synthesis/clr.fse
clr/synthesis/clr.szr
clr/synthesis/clr.srd
clr/synthesis/clr.srm
clr/synthesis/clr.map
clr/synthesis/clr.edn
clr/synthesis/clr.sdf
clr/synthesis/clr.pdc
clr/synthesis/clr_sdc.sdc
clr/synthesis/clr.so
clr/synthesis/clr.areasrr
clr/synthesis/clr.vhd
clr/synthesis/clr_syn.prj
clr/synthesis/clr.srr
clr/synthesis/identify.log
clr/synthesis/clr.srs
clr/stimulus/sys_init.hpj
clr/stimulus/waveperl.log
clr/stimulus/BtimErrors.log
clr/stimulus/files_to_build.txt
clr/stimulus/sys_init_tbench.btim
clr/stimulus/sys_init_tbench.vhd
clr/stimulus/sys_init_tbench.bk
clr/stimulus/sys_init.dsk
clr/stimulus/clr.hpj
clr/stimulus/clr_tbench.btim
clr/stimulus/clr_tbench.vhd
clr/stimulus/clr.dsk
clr/designer/impl1/sys_init.ide_des
clr/designer/impl1/sys_init.tcl
clr/designer/impl1/designer_synth_check.log
clr/designer/impl1/sys_init.dtf/verify.log
clr/designer/impl1/sys_init.pdb
clr/designer/impl1/sys_init.pdb.depends
clr/designer/impl1/designer.log
clr/designer/impl1/sys_init_fp/sys_init.pro
clr/designer/impl1/sys_init_fp/$$FlashPro_10438.L$$
clr/designer/impl1/sys_init_fp/projectData/sys_init.pdb
clr/designer/impl1/sys_init_fp/sys_init.log
clr/designer/impl1/sys_init.adb
clr/designer/impl1/clr.ide_des
clr/designer/impl1/clr.tcl
clr/designer/impl1/clr.dtf/verify.log
clr/designer/impl1/clr.pdb
clr/designer/impl1/clr.pdb.depends
clr/designer/impl1/clr.adb
clr/designer/impl1/clr_fp/clr.pro
clr/designer/impl1/clr_fp/$$FlashPro_10438.L$$
clr/designer/impl1/clr_fp/clr.log
clr/clr.prj
clr/designer/impl1/sys_init_fp/projectData
clr/simulation/postsynth/_temp
clr/simulation/postsynth/sys_init
clr/simulation/postsynth/stimulus
clr/simulation/postsynth/testbench
clr/simulation/postsynth/clr
clr/designer/impl1/simulation
clr/designer/impl1/sys_init.dtf
clr/designer/impl1/sys_init_fp
clr/designer/impl1/clr.dtf
clr/designer/impl1/clr_fp
clr/viewdraw/vf
clr/viewdraw/sch
clr/viewdraw/sym
clr/viewdraw/wir
clr/simulation/postsynth
clr/synthesis/syntmp
clr/synthesis/coreip
clr/synthesis/xplace
clr/synthesis/backup
clr/designer/impl1
clr/smartgen
clr/hdl
clr/constraint
clr/viewdraw
clr/component
clr/coreconsole
clr/simulation
clr/synthesis
clr/phy_synthesis
clr/stimulus
clr/designer
clr
clr/hdl/clr.vhd
clr/viewdraw/vf/project.lst
clr/viewdraw/viewdraw.ini
clr/simulation/run.do
clr/simulation/modelsim.log
clr/simulation/postsynth/_info
clr/simulation/postsynth/_vmake
clr/simulation/postsynth/sys_init/_primary.dbs
clr/simulation/postsynth/sys_init/_primary.dat
clr/simulation/postsynth/sys_init/def_arch.dbs
clr/simulation/postsynth/sys_init/def_arch.dat
clr/simulation/postsynth/sys_init/def_arch.psm
clr/simulation/postsynth/sys_init/def_arch.prw
clr/simulation/postsynth/stimulus/stimulator.psm
clr/simulation/postsynth/stimulus/stimulator.prw
clr/simulation/postsynth/stimulus/_primary.dbs
clr/simulation/postsynth/stimulus/_primary.dat
clr/simulation/postsynth/stimulus/stimulator.dbs
clr/simulation/postsynth/stimulus/stimulator.dat
clr/simulation/postsynth/testbench/tbgeneratedcode.psm
clr/simulation/postsynth/testbench/tbgeneratedcode.prw
clr/simulation/postsynth/testbench/_primary.dbs
clr/simulation/postsynth/testbench/_primary.dat
clr/simulation/postsynth/testbench/tbgeneratedcode.dbs
clr/simulation/postsynth/testbench/tbgeneratedcode.dat
clr/simulation/postsynth/clr/def_arch.psm
clr/simulation/postsynth/clr/def_arch.prw
clr/simulation/postsynth/clr/_primary.dbs
clr/simulation/postsynth/clr/_primary.dat
clr/simulation/postsynth/clr/def_arch.dbs
clr/simulation/postsynth/clr/def_arch.dat
clr/simulation/tb.log
clr/simulation/vsim.wlf
clr/simulation/modelsim.ini.sav
clr/simulation/modelsim.ini
clr/simulation/wave.do
clr/synthesis/stdout.log
clr/synthesis/syntmp/sys_init_flink.htm
clr/synthesis/syntmp/sys_init_srr.htm
clr/synthesis/syntmp/sys_init_toc.htm
clr/synthesis/syntmp/sap.log
clr/synthesis/syntmp/sys_init.plg
clr/synthesis/syntmp/sap_log_flink.htm
clr/synthesis/syntmp/sap_log_srr.htm
clr/synthesis/syntmp/sys_init.msg
clr/synthesis/syntmp/clr_flink.htm
clr/synthesis/syntmp/clr_srr.htm
clr/synthesis/syntmp/clr_toc.htm
clr/synthesis/syntmp/clr.plg
clr/synthesis/syntmp/clr.msg
clr/synthesis/backup/sys_init.srr
clr/synthesis/backup/clr.srr
clr/synthesis/run_options.txt
clr/synthesis/scratchproject.prs
clr/synthesis/sys_init.so
clr/synthesis/sys_init.htm
clr/synthesis/sys_init.tlg
clr/synthesis/.recordref
clr/synthesis/sys_init.srl
clr/synthesis/sys_init.sap
clr/synthesis/sys_init.fse
clr/synthesis/sys_init.szr
clr/synthesis/sys_init.srd
clr/synthesis/sys_init.srm
clr/synthesis/sys_init.map
clr/synthesis/sys_init.edn
clr/synthesis/sys_init.sdf
clr/synthesis/sys_init.pdc
clr/synthesis/sys_init_sdc.sdc
clr/synthesis/sys_init.areasrr
clr/synthesis/sys_init.vhd
clr/synthesis/sys_init_syn.prj
clr/synthesis/sys_init.srr
clr/synthesis/sys_init.srs
clr/synthesis/clr.tlg
clr/synthesis/clr.srl
clr/synthesis/clr.htm
clr/synthesis/clr.sap
clr/synthesis/clr.fse
clr/synthesis/clr.szr
clr/synthesis/clr.srd
clr/synthesis/clr.srm
clr/synthesis/clr.map
clr/synthesis/clr.edn
clr/synthesis/clr.sdf
clr/synthesis/clr.pdc
clr/synthesis/clr_sdc.sdc
clr/synthesis/clr.so
clr/synthesis/clr.areasrr
clr/synthesis/clr.vhd
clr/synthesis/clr_syn.prj
clr/synthesis/clr.srr
clr/synthesis/identify.log
clr/synthesis/clr.srs
clr/stimulus/sys_init.hpj
clr/stimulus/waveperl.log
clr/stimulus/BtimErrors.log
clr/stimulus/files_to_build.txt
clr/stimulus/sys_init_tbench.btim
clr/stimulus/sys_init_tbench.vhd
clr/stimulus/sys_init_tbench.bk
clr/stimulus/sys_init.dsk
clr/stimulus/clr.hpj
clr/stimulus/clr_tbench.btim
clr/stimulus/clr_tbench.vhd
clr/stimulus/clr.dsk
clr/designer/impl1/sys_init.ide_des
clr/designer/impl1/sys_init.tcl
clr/designer/impl1/designer_synth_check.log
clr/designer/impl1/sys_init.dtf/verify.log
clr/designer/impl1/sys_init.pdb
clr/designer/impl1/sys_init.pdb.depends
clr/designer/impl1/designer.log
clr/designer/impl1/sys_init_fp/sys_init.pro
clr/designer/impl1/sys_init_fp/$$FlashPro_10438.L$$
clr/designer/impl1/sys_init_fp/projectData/sys_init.pdb
clr/designer/impl1/sys_init_fp/sys_init.log
clr/designer/impl1/sys_init.adb
clr/designer/impl1/clr.ide_des
clr/designer/impl1/clr.tcl
clr/designer/impl1/clr.dtf/verify.log
clr/designer/impl1/clr.pdb
clr/designer/impl1/clr.pdb.depends
clr/designer/impl1/clr.adb
clr/designer/impl1/clr_fp/clr.pro
clr/designer/impl1/clr_fp/$$FlashPro_10438.L$$
clr/designer/impl1/clr_fp/clr.log
clr/clr.prj
clr/designer/impl1/sys_init_fp/projectData
clr/simulation/postsynth/_temp
clr/simulation/postsynth/sys_init
clr/simulation/postsynth/stimulus
clr/simulation/postsynth/testbench
clr/simulation/postsynth/clr
clr/designer/impl1/simulation
clr/designer/impl1/sys_init.dtf
clr/designer/impl1/sys_init_fp
clr/designer/impl1/clr.dtf
clr/designer/impl1/clr_fp
clr/viewdraw/vf
clr/viewdraw/sch
clr/viewdraw/sym
clr/viewdraw/wir
clr/simulation/postsynth
clr/synthesis/syntmp
clr/synthesis/coreip
clr/synthesis/xplace
clr/synthesis/backup
clr/designer/impl1
clr/smartgen
clr/hdl
clr/constraint
clr/viewdraw
clr/component
clr/coreconsole
clr/simulation
clr/synthesis
clr/phy_synthesis
clr/stimulus
clr/designer
clr
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