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文件名称:i2c
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- 上传时间:2012-11-16
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文件大小:1.45mb
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介绍说明--下载内容来自于网络,使用问题请自行百度
这是一个 OPENCORES的I2C MASTER CORE,非常实用-This is a core from opencores,and it is very useful
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c/
i2c/branches/
i2c/tags/
i2c/tags/asyst_2/
i2c/tags/asyst_2/rtl/
i2c/tags/asyst_2/rtl/verilog/
i2c/tags/asyst_2/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_defines.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
i2c/tags/asyst_2/rtl/verilog/timescale.v
i2c/tags/asyst_3/
i2c/tags/asyst_3/rtl/
i2c/tags/asyst_3/rtl/verilog/
i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_defines.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_top.v
i2c/tags/asyst_3/rtl/verilog/timescale.v
i2c/tags/first/
i2c/tags/first/I2C.VHD
i2c/tags/first/tst_ds1621.vhd
i2c/tags/rel_1/
i2c/tags/rel_1/bench/
i2c/tags/rel_1/bench/verilog/
i2c/tags/rel_1/bench/verilog/i2c_slave_model.v
i2c/tags/rel_1/bench/verilog/tst_bench_top.v
i2c/tags/rel_1/bench/verilog/wb_master_model.v
i2c/tags/rel_1/doc/
i2c/tags/rel_1/doc/i2c_specs.pdf
i2c/tags/rel_1/doc/src/
i2c/tags/rel_1/doc/src/I2C_specs.doc
i2c/tags/rel_1/rtl/
i2c/tags/rel_1/rtl/verilog/
i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/rel_1/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/rel_1/rtl/verilog/i2c_master_defines.v
i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
i2c/tags/rel_1/rtl/verilog/timescale.v
i2c/tags/rel_1/rtl/vhdl/
i2c/tags/rel_1/rtl/vhdl/I2C.VHD
i2c/tags/rel_1/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/tags/rel_1/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/tags/rel_1/rtl/vhdl/i2c_master_top.vhd
i2c/tags/rel_1/rtl/vhdl/readme
i2c/tags/rel_1/rtl/vhdl/tst_ds1621.vhd
i2c/tags/rel_1/sim/
i2c/tags/rel_1/sim/i2c_verilog/
i2c/tags/rel_1/sim/i2c_verilog/run/
i2c/tags/rel_1/sim/i2c_verilog/run/bench.vcd
i2c/tags/rel_1/sim/i2c_verilog/run/ncverilog.key
i2c/tags/rel_1/sim/i2c_verilog/run/ncverilog.log
i2c/tags/rel_1/sim/i2c_verilog/run/run
i2c/tags/rel_1/software/
i2c/tags/rel_1/software/include/
i2c/tags/rel_1/software/include/oc_i2c_master.h
i2c/trunk/
i2c/trunk/bench/
i2c/trunk/bench/verilog/
i2c/trunk/bench/verilog/i2c_slave_model.v
i2c/trunk/bench/verilog/spi_slave_model.v
i2c/trunk/bench/verilog/tst_bench_top.v
i2c/trunk/bench/verilog/wb_master_model.v
i2c/trunk/doc/
i2c/trunk/doc/i2c_specs.pdf
i2c/trunk/doc/src/
i2c/trunk/doc/src/I2C_specs.doc
i2c/trunk/rtl/
i2c/trunk/rtl/verilog/
i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
i2c/trunk/rtl/verilog/i2c_master_defines.v
i2c/trunk/rtl/verilog/i2c_master_top.v
i2c/trunk/rtl/verilog/timescale.v
i2c/trunk/rtl/vhdl/
i2c/trunk/rtl/vhdl/I2C.VHD
i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/trunk/rtl/vhdl/i2c_master_top.vhd
i2c/trunk/rtl/vhdl/readme
i2c/trunk/rtl/vhdl/tst_ds1621.vhd
i2c/trunk/sim/
i2c/trunk/sim/i2c_verilog/
i2c/trunk/sim/i2c_verilog/run/
i2c/trunk/sim/i2c_verilog/run/bench.vcd
i2c/trunk/sim/i2c_verilog/run/ncverilog.key
i2c/trunk/sim/i2c_verilog/run/ncverilog.log
i2c/trunk/sim/i2c_verilog/run/run
i2c/trunk/software/
i2c/trunk/software/include/
i2c/trunk/software/include/oc_i2c_master.h
i2c/web_uploads/
i2c/web_uploads/Block.gif
i2c/web_uploads/i2c_rev03.pdf
i2c/web_uploads/index.shtml
i2c/web_uploads/index_orig.shtml
i2c/branches/
i2c/tags/
i2c/tags/asyst_2/
i2c/tags/asyst_2/rtl/
i2c/tags/asyst_2/rtl/verilog/
i2c/tags/asyst_2/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_defines.v
i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
i2c/tags/asyst_2/rtl/verilog/timescale.v
i2c/tags/asyst_3/
i2c/tags/asyst_3/rtl/
i2c/tags/asyst_3/rtl/verilog/
i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_defines.v
i2c/tags/asyst_3/rtl/verilog/i2c_master_top.v
i2c/tags/asyst_3/rtl/verilog/timescale.v
i2c/tags/first/
i2c/tags/first/I2C.VHD
i2c/tags/first/tst_ds1621.vhd
i2c/tags/rel_1/
i2c/tags/rel_1/bench/
i2c/tags/rel_1/bench/verilog/
i2c/tags/rel_1/bench/verilog/i2c_slave_model.v
i2c/tags/rel_1/bench/verilog/tst_bench_top.v
i2c/tags/rel_1/bench/verilog/wb_master_model.v
i2c/tags/rel_1/doc/
i2c/tags/rel_1/doc/i2c_specs.pdf
i2c/tags/rel_1/doc/src/
i2c/tags/rel_1/doc/src/I2C_specs.doc
i2c/tags/rel_1/rtl/
i2c/tags/rel_1/rtl/verilog/
i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
i2c/tags/rel_1/rtl/verilog/i2c_master_byte_ctrl.v
i2c/tags/rel_1/rtl/verilog/i2c_master_defines.v
i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
i2c/tags/rel_1/rtl/verilog/timescale.v
i2c/tags/rel_1/rtl/vhdl/
i2c/tags/rel_1/rtl/vhdl/I2C.VHD
i2c/tags/rel_1/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/tags/rel_1/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/tags/rel_1/rtl/vhdl/i2c_master_top.vhd
i2c/tags/rel_1/rtl/vhdl/readme
i2c/tags/rel_1/rtl/vhdl/tst_ds1621.vhd
i2c/tags/rel_1/sim/
i2c/tags/rel_1/sim/i2c_verilog/
i2c/tags/rel_1/sim/i2c_verilog/run/
i2c/tags/rel_1/sim/i2c_verilog/run/bench.vcd
i2c/tags/rel_1/sim/i2c_verilog/run/ncverilog.key
i2c/tags/rel_1/sim/i2c_verilog/run/ncverilog.log
i2c/tags/rel_1/sim/i2c_verilog/run/run
i2c/tags/rel_1/software/
i2c/tags/rel_1/software/include/
i2c/tags/rel_1/software/include/oc_i2c_master.h
i2c/trunk/
i2c/trunk/bench/
i2c/trunk/bench/verilog/
i2c/trunk/bench/verilog/i2c_slave_model.v
i2c/trunk/bench/verilog/spi_slave_model.v
i2c/trunk/bench/verilog/tst_bench_top.v
i2c/trunk/bench/verilog/wb_master_model.v
i2c/trunk/doc/
i2c/trunk/doc/i2c_specs.pdf
i2c/trunk/doc/src/
i2c/trunk/doc/src/I2C_specs.doc
i2c/trunk/rtl/
i2c/trunk/rtl/verilog/
i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
i2c/trunk/rtl/verilog/i2c_master_defines.v
i2c/trunk/rtl/verilog/i2c_master_top.v
i2c/trunk/rtl/verilog/timescale.v
i2c/trunk/rtl/vhdl/
i2c/trunk/rtl/vhdl/I2C.VHD
i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/trunk/rtl/vhdl/i2c_master_top.vhd
i2c/trunk/rtl/vhdl/readme
i2c/trunk/rtl/vhdl/tst_ds1621.vhd
i2c/trunk/sim/
i2c/trunk/sim/i2c_verilog/
i2c/trunk/sim/i2c_verilog/run/
i2c/trunk/sim/i2c_verilog/run/bench.vcd
i2c/trunk/sim/i2c_verilog/run/ncverilog.key
i2c/trunk/sim/i2c_verilog/run/ncverilog.log
i2c/trunk/sim/i2c_verilog/run/run
i2c/trunk/software/
i2c/trunk/software/include/
i2c/trunk/software/include/oc_i2c_master.h
i2c/web_uploads/
i2c/web_uploads/Block.gif
i2c/web_uploads/i2c_rev03.pdf
i2c/web_uploads/index.shtml
i2c/web_uploads/index_orig.shtml
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