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文件名称:ddr2_demo
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文件大小:866.11kb
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lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ddr2_demo/user_logic/testbench/ddr2_demo_tb.v
ddr2_demo/user_logic/src/ddr2_demo_top.v
ddr2_demo/user_logic/src/ddr_ulogic.v
ddr2_demo/user_logic/src/lfsr128.v
ddr2_demo/user_logic/sim/modelsim/ddr2_ecp3_demo.do
ddr2_demo/user_logic/sim/modelsim/wave.do
ddr2_demo/user_logic/sim/aldec/ddr2_ecp3_demo.do
ddr2_demo/user_logic/sim/aldec/wave.do
ddr2_demo/user_logic/par/ddr2_ecp3_spb.ldf
ddr2_demo/user_logic/par/ddr2_ecp3_spb.lpf
ddr2_demo/user_logic/par/ddr2_ecp3_spb.pty
ddr2_demo/user_logic/par/Strategy1.sty
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1_summary.html
ddr2_demo/user_logic/par/impl1/launch_synplify.tcl
ddr2_demo/user_logic/par/impl1/stdout.log
ddr2_demo/user_logic/par/impl1/impl1_syn.prj
ddr2_demo/user_logic/par/impl1/syntmp/run_option.xml
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_compiler.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1_flink.htm
ddr2_demo/user_logic/par/impl1/syntmp/impl1_srr.htm
ddr2_demo/user_logic/par/impl1/syntmp/impl1_toc.htm
ddr2_demo/user_logic/par/impl1/syntmp/closed.png
ddr2_demo/user_logic/par/impl1/syntmp/open.png
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_premap.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1.plg
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_fpga_mapper.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1.msg
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_errors.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_errors.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_generated_clk.rpt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_timing_report.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_area_report.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_opt_report.xml
ddr2_demo/user_logic/par/impl1/synlog/impl1_premap.srr
ddr2_demo/user_logic/par/impl1/synlog/impl1_premap.szr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.srr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.szr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.srr_Min
ddr2_demo/user_logic/par/impl1/synwork/impl1_compiler.tlg
ddr2_demo/user_logic/par/impl1/synwork/impl1_compiler.srs
ddr2_demo/user_logic/par/impl1/synwork/impl1_premap.fse
ddr2_demo/user_logic/par/impl1/synwork/impl1_premap.srd
ddr2_demo/user_logic/par/impl1/run_options.txt
ddr2_demo/user_logic/par/impl1/scratchproject.prs
ddr2_demo/user_logic/par/impl1/impl1.srr
ddr2_demo/user_logic/par/impl1/dm/impl1_compiler.xdm
ddr2_demo/user_logic/par/impl1/impl1.srl
ddr2_demo/user_logic/par/impl1/impl1.srs
ddr2_demo/user_logic/par/impl1/impl1.htm
ddr2_demo/user_logic/par/impl1/impl1_scck.rpt
ddr2_demo/user_logic/par/impl1/impl1.szr
ddr2_demo/user_logic/par/impl1/impl1.fse
ddr2_demo/user_logic/par/impl1/traplog.tlg
ddr2_demo/user_logic/par/impl1/.recordref_modgen
ddr2_demo/user_logic/par/impl1/AutoConstraint_ddr2_demo_top.sdc
ddr2_demo/user_logic/par/impl1/impl1.srd
ddr2_demo/user_logic/par/impl1/impl1.srm
ddr2_demo/user_logic/par/impl1/impl1.edi
ddr2_demo/user_logic/par/impl1/impl1_synplify.lpf
ddr2_demo/user_logic/par/impl1/impl1.areasrr
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1.edi
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1.areasrr
ddr2_demo/user_logic/par/impl1/.build_status
ddr2_demo/user_logic/par/reportview.xml
ddr2_demo/user_logic/par/.spreadsheet_view.ini
ddr2_demo/user_logic/par/.run_manager.ini
ddr2_demo/user_logic/par/ddr2_ecp3_spb.ccl
ddr2_demo/user_logic/par/.spread_sheet.ini
ddr2_demo/resource/doc/readme.txt
ddr2_demo/resource/bitstream/95EA/ddr2_ecp3_spb_impl1.bit
ddr2_demo/core/ddr2_ecp3.ipx
ddr2_demo/core/ddr2_ecp3.lpc
ddr2_demo/core/ddr2_ecp3.ngo
ddr2_demo/core/ddr2_ecp3_bb.v
ddr2_demo/core/ddr2_ecp3_beh.v
ddr2_demo/core/ddr2_ecp3_filelist.log
ddr2_demo/core/ddr2_ecp3_gen.log
ddr2_demo/core/ddr2_ecp3_generate.log
ddr2_demo/core/ddr2_ecp3_inst.v
ddr2_demo/core/ddr_sdram_mem_params.v
ddr2_demo/core/generate_core.tcl
ddr2_demo/core/ddr_p_eval/eval_sim_readme.txt
ddr2_demo/core/ddr_p_eval/readme.htm
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/monitor.v
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/odt_watchdog.v
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/test_mem_ctrl.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/cmd_gen.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/tb_config_params.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/testcase.v
ddr2_demo/core/ddr_p_eval/mod
ddr2_demo/user_logic/src/ddr2_demo_top.v
ddr2_demo/user_logic/src/ddr_ulogic.v
ddr2_demo/user_logic/src/lfsr128.v
ddr2_demo/user_logic/sim/modelsim/ddr2_ecp3_demo.do
ddr2_demo/user_logic/sim/modelsim/wave.do
ddr2_demo/user_logic/sim/aldec/ddr2_ecp3_demo.do
ddr2_demo/user_logic/sim/aldec/wave.do
ddr2_demo/user_logic/par/ddr2_ecp3_spb.ldf
ddr2_demo/user_logic/par/ddr2_ecp3_spb.lpf
ddr2_demo/user_logic/par/ddr2_ecp3_spb.pty
ddr2_demo/user_logic/par/Strategy1.sty
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1_summary.html
ddr2_demo/user_logic/par/impl1/launch_synplify.tcl
ddr2_demo/user_logic/par/impl1/stdout.log
ddr2_demo/user_logic/par/impl1/impl1_syn.prj
ddr2_demo/user_logic/par/impl1/syntmp/run_option.xml
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_compiler.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1_flink.htm
ddr2_demo/user_logic/par/impl1/syntmp/impl1_srr.htm
ddr2_demo/user_logic/par/impl1/syntmp/impl1_toc.htm
ddr2_demo/user_logic/par/impl1/syntmp/closed.png
ddr2_demo/user_logic/par/impl1/syntmp/open.png
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_premap.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1.plg
ddr2_demo/user_logic/par/impl1/syntmp/cmdrec_fpga_mapper.log
ddr2_demo/user_logic/par/impl1/syntmp/impl1.msg
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_compiler_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_errors.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_premap_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_errors.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_warnings.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_notes.txt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_runstatus.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_generated_clk.rpt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_timing_report.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_area_report.xml
ddr2_demo/user_logic/par/impl1/synlog/report/impl1_fpga_mapper_opt_report.xml
ddr2_demo/user_logic/par/impl1/synlog/impl1_premap.srr
ddr2_demo/user_logic/par/impl1/synlog/impl1_premap.szr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.srr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.szr
ddr2_demo/user_logic/par/impl1/synlog/impl1_fpga_mapper.srr_Min
ddr2_demo/user_logic/par/impl1/synwork/impl1_compiler.tlg
ddr2_demo/user_logic/par/impl1/synwork/impl1_compiler.srs
ddr2_demo/user_logic/par/impl1/synwork/impl1_premap.fse
ddr2_demo/user_logic/par/impl1/synwork/impl1_premap.srd
ddr2_demo/user_logic/par/impl1/run_options.txt
ddr2_demo/user_logic/par/impl1/scratchproject.prs
ddr2_demo/user_logic/par/impl1/impl1.srr
ddr2_demo/user_logic/par/impl1/dm/impl1_compiler.xdm
ddr2_demo/user_logic/par/impl1/impl1.srl
ddr2_demo/user_logic/par/impl1/impl1.srs
ddr2_demo/user_logic/par/impl1/impl1.htm
ddr2_demo/user_logic/par/impl1/impl1_scck.rpt
ddr2_demo/user_logic/par/impl1/impl1.szr
ddr2_demo/user_logic/par/impl1/impl1.fse
ddr2_demo/user_logic/par/impl1/traplog.tlg
ddr2_demo/user_logic/par/impl1/.recordref_modgen
ddr2_demo/user_logic/par/impl1/AutoConstraint_ddr2_demo_top.sdc
ddr2_demo/user_logic/par/impl1/impl1.srd
ddr2_demo/user_logic/par/impl1/impl1.srm
ddr2_demo/user_logic/par/impl1/impl1.edi
ddr2_demo/user_logic/par/impl1/impl1_synplify.lpf
ddr2_demo/user_logic/par/impl1/impl1.areasrr
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1.edi
ddr2_demo/user_logic/par/impl1/ddr2_ecp3_spb_impl1.areasrr
ddr2_demo/user_logic/par/impl1/.build_status
ddr2_demo/user_logic/par/reportview.xml
ddr2_demo/user_logic/par/.spreadsheet_view.ini
ddr2_demo/user_logic/par/.run_manager.ini
ddr2_demo/user_logic/par/ddr2_ecp3_spb.ccl
ddr2_demo/user_logic/par/.spread_sheet.ini
ddr2_demo/resource/doc/readme.txt
ddr2_demo/resource/bitstream/95EA/ddr2_ecp3_spb_impl1.bit
ddr2_demo/core/ddr2_ecp3.ipx
ddr2_demo/core/ddr2_ecp3.lpc
ddr2_demo/core/ddr2_ecp3.ngo
ddr2_demo/core/ddr2_ecp3_bb.v
ddr2_demo/core/ddr2_ecp3_beh.v
ddr2_demo/core/ddr2_ecp3_filelist.log
ddr2_demo/core/ddr2_ecp3_gen.log
ddr2_demo/core/ddr2_ecp3_generate.log
ddr2_demo/core/ddr2_ecp3_inst.v
ddr2_demo/core/ddr_sdram_mem_params.v
ddr2_demo/core/generate_core.tcl
ddr2_demo/core/ddr_p_eval/eval_sim_readme.txt
ddr2_demo/core/ddr_p_eval/readme.htm
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/monitor.v
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/odt_watchdog.v
ddr2_demo/core/ddr_p_eval/testbench/top/ecp3/test_mem_ctrl.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/cmd_gen.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/tb_config_params.v
ddr2_demo/core/ddr_p_eval/testbench/tests/ecp3/testcase.v
ddr2_demo/core/ddr_p_eval/mod
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