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文件名称:sdram_control
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- 上传时间:2012-11-16
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文件大小:2.66mb
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介绍说明--下载内容来自于网络,使用问题请自行百度
该代码主要实现了对静态sram的控制,分为三个模块,控制部分,数据产生路径部分,实现了对sram的写入与读出操作。-The code is mainly to achieve the static SRAM control, is divided into three modules, control, data generating portion of the path, SRAM implementation of write and read operations.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sdram_control/doc/read_me.doc
sdram_control/doc/SDRAM.doc
sdram_control/doc/sdr_sdram.pdf
sdram_control/sim/altera_mf.qpf
sdram_control/sim/altera_mf.qsf
sdram_control/sim/altera_mf.qws
sdram_control/sim/altera_mf.v
sdram_control/sim/Command.v
sdram_control/sim/control_interface.v
sdram_control/sim/db/altera_mf.db_info
sdram_control/sim/db/altera_mf.eco.cdb
sdram_control/sim/db/altera_mf.sld_design_entry.sci
sdram_control/sim/mt48lc2m32b2.v
sdram_control/sim/Params.v
sdram_control/sim/sdram_test.cr.mti
sdram_control/sim/sdram_test.mpf
sdram_control/sim/sdram_test.wlf
sdram_control/sim/sdram_test_tb.v
sdram_control/sim/transcript
sdram_control/sim/vsim.wlf
sdram_control/sim/wave.do
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
sdram_control/sim/work/@m@f_pll_reg/verilog.asm
sdram_control/sim/work/@m@f_pll_reg/_primary.dat
sdram_control/sim/work/@m@f_pll_reg/_primary.vhd
sdram_control/sim/work/@m@f_ram7x20_syn/verilog.asm
sdram_control/sim/work/@m@f_ram7x20_syn/_primary.dat
sdram_control/sim/work/@m@f_ram7x20_syn/_primary.vhd
sdram_control/sim/work/@m@f_stratixii_pll/verilog.asm
sdram_control/sim/work/@m@f_stratixii_pll/_primary.dat
sdram_control/sim/work/@m@f_stratixii_pll/_primary.vhd
sdram_control/sim/work/@m@f_stratix_pll/verilog.asm
sdram_control/sim/work/@m@f_stratix_pll/_primary.dat
sdram_control/sim/work/@m@f_stratix_pll/_primary.vhd
sdram_control/sim/work/alt3pram/verilog.asm
sdram_control/sim/work/alt3pram/_primary.dat
sdram_control/sim/work/alt3pram/_primary.vhd
sdram_control/sim/work/altaccumulate/verilog.asm
sdram_control/sim/work/altaccumulate/_primary.dat
sdram_control/sim/work/altaccumulate/_primary.vhd
sdram_control/sim/work/altcam/verilog.asm
sdram_control/sim/work/altcam/_primary.dat
sdram_control/sim/work/altcam/_primary.vhd
sdram_control/sim/work/altcdr_rx/verilog.asm
sdram_control/sim/work/altcdr_rx/_primary.dat
sdram_control/sim/work/altcdr_rx/_primary.vhd
sdram_control/sim/work/altcdr_tx/verilog.asm
sdram_control/sim/work/altcdr_tx/_primary.dat
sdram_control/sim/work/altcdr_tx/_primary.vhd
sdram_control/sim/work/altclklock/verilog.asm
sdram_control/sim/work/altclklock/_primary.dat
sdram_control/sim/work/altclklock/_primary.vhd
sdram_control/sim/work/altddio_bidir/verilog.asm
sdram_control/sim/work/altddio_bidir/_primary.dat
sdram_control/sim/work/altddio_bidir/_primary.vhd
sdram_control/sim/work/altddio_in/verilog.asm
sdram_control/sim/work/altddio_in/_primary.dat
sdram_control/sim/work/altddio_in/_primary.vhd
sdram_control/sim/work/altddio_out/verilog.asm
sdram_control/sim/work/altddio_out/_primary.dat
sdram_control/sim/work/altddio_out/_primary.vhd
sdram_control/sim/work/altdpram/verilog.asm
sdram_control/sim/work/altdpram/_primary.dat
sdram_control/sim/work/altdpram/_primary.vhd
sdram_control/sim/work/altfp_mult/verilog.asm
sdram_control/sim/work/altfp_mult/_primary.dat
sdram_control/sim/work/altfp_mult/_primary.vhd
sdram_control/sim/work/altlvds_rx/verilog.asm
sdram_control/sim/work/altlvds_rx/_primary.dat
sdram_control/sim/work/altlvds_rx/_primary.vhd
sdram_control/sim/work/altlvds_tx/verilog.asm
sdram_control/sim/work/altlvds_tx/_primary.dat
sdram_control/sim/work/altlvds_tx/_primary.vhd
sdram_control/sim/work/altmult_accum/verilog.asm
sdram_control/sim/work/altmult_accum/_primary.dat
sdram_control/sim/work/altmult_accum/_primary.vhd
sdram_control/sim/work/altmult_add/verilog.asm
sdram_control/sim/work/altmult_add/_primary.dat
sdram_control/sim/work/altmult_add/_primary.vhd
sdram_control/sim/work/altpll/verilog.asm
sdram_control/sim/work/altpll/_primary.dat
sdram_control/sim/work/altpll/_primary.vhd
sdram_control/sim/work/altqpram/verilog.asm
sdram_control/sim/work/altqpram/_primary.dat
sdram_control/sim/work/altqpram/_primary.vhd
sdram_control/sim/work/altshift_taps/verilog.asm
sdram_control/sim/work/altshift_taps/_primary.dat
sdram_control/sim/work/altshift_taps/_primary.vhd
sdram_control/sim/work/altsqrt/verilog.asm
sdram_control/sim/work/altsqrt/_primary.dat
sdram_control/sim/work/altsqrt/_primary.vhd
sdram_control/sim/work/altsyncram/verilog.asm
sdram_control/sim/work/altsyncram/_primary.dat
sdram_control/sim/work/altsyncram/_primary.vhd
sdram_control/sim/work/alt_exc_dpram/verilog.asm
sdram_control/sim/work/alt_exc_dpram/_primary.dat
sdram_control/sim/work/alt_exc_dpram/_primary.vhd
sdram_control/sim/work/alt_exc_upcore/verilog.asm
sdram_control/sim/work/alt_exc_upcore/_primary.dat
sdram_control/sim/work/alt_exc_upcore/_primary.vhd
sdram_control/sim/work/arm_m_cntr/verilog.asm
sdram_control/sim/work/arm_m_cntr/_primary.dat
sdram_control/sim/work/arm_m_cntr/_primary.vhd
sdram_control/sim/work/arm_n_cntr/verilog.asm
sdram_control/sim/work/arm_n_cntr/_primary.dat
sdram_control/sim/work/arm_n_cntr/_primary.vhd
sdram_control/sim/work/arm_scale_cntr/verilog.asm
sdram_control/sim/work/arm_scale_cntr/_primary.dat
sdram_control/sim/work/arm_scale_cntr/_primary.vhd
sdram_control/sim/work/a_graycounter/verilog.asm
s
sdram_control/doc/SDRAM.doc
sdram_control/doc/sdr_sdram.pdf
sdram_control/sim/altera_mf.qpf
sdram_control/sim/altera_mf.qsf
sdram_control/sim/altera_mf.qws
sdram_control/sim/altera_mf.v
sdram_control/sim/Command.v
sdram_control/sim/control_interface.v
sdram_control/sim/db/altera_mf.db_info
sdram_control/sim/db/altera_mf.eco.cdb
sdram_control/sim/db/altera_mf.sld_design_entry.sci
sdram_control/sim/mt48lc2m32b2.v
sdram_control/sim/Params.v
sdram_control/sim/sdram_test.cr.mti
sdram_control/sim/sdram_test.mpf
sdram_control/sim/sdram_test.wlf
sdram_control/sim/sdram_test_tb.v
sdram_control/sim/transcript
sdram_control/sim/vsim.wlf
sdram_control/sim/wave.do
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
sdram_control/sim/work/@m@f_pll_reg/verilog.asm
sdram_control/sim/work/@m@f_pll_reg/_primary.dat
sdram_control/sim/work/@m@f_pll_reg/_primary.vhd
sdram_control/sim/work/@m@f_ram7x20_syn/verilog.asm
sdram_control/sim/work/@m@f_ram7x20_syn/_primary.dat
sdram_control/sim/work/@m@f_ram7x20_syn/_primary.vhd
sdram_control/sim/work/@m@f_stratixii_pll/verilog.asm
sdram_control/sim/work/@m@f_stratixii_pll/_primary.dat
sdram_control/sim/work/@m@f_stratixii_pll/_primary.vhd
sdram_control/sim/work/@m@f_stratix_pll/verilog.asm
sdram_control/sim/work/@m@f_stratix_pll/_primary.dat
sdram_control/sim/work/@m@f_stratix_pll/_primary.vhd
sdram_control/sim/work/alt3pram/verilog.asm
sdram_control/sim/work/alt3pram/_primary.dat
sdram_control/sim/work/alt3pram/_primary.vhd
sdram_control/sim/work/altaccumulate/verilog.asm
sdram_control/sim/work/altaccumulate/_primary.dat
sdram_control/sim/work/altaccumulate/_primary.vhd
sdram_control/sim/work/altcam/verilog.asm
sdram_control/sim/work/altcam/_primary.dat
sdram_control/sim/work/altcam/_primary.vhd
sdram_control/sim/work/altcdr_rx/verilog.asm
sdram_control/sim/work/altcdr_rx/_primary.dat
sdram_control/sim/work/altcdr_rx/_primary.vhd
sdram_control/sim/work/altcdr_tx/verilog.asm
sdram_control/sim/work/altcdr_tx/_primary.dat
sdram_control/sim/work/altcdr_tx/_primary.vhd
sdram_control/sim/work/altclklock/verilog.asm
sdram_control/sim/work/altclklock/_primary.dat
sdram_control/sim/work/altclklock/_primary.vhd
sdram_control/sim/work/altddio_bidir/verilog.asm
sdram_control/sim/work/altddio_bidir/_primary.dat
sdram_control/sim/work/altddio_bidir/_primary.vhd
sdram_control/sim/work/altddio_in/verilog.asm
sdram_control/sim/work/altddio_in/_primary.dat
sdram_control/sim/work/altddio_in/_primary.vhd
sdram_control/sim/work/altddio_out/verilog.asm
sdram_control/sim/work/altddio_out/_primary.dat
sdram_control/sim/work/altddio_out/_primary.vhd
sdram_control/sim/work/altdpram/verilog.asm
sdram_control/sim/work/altdpram/_primary.dat
sdram_control/sim/work/altdpram/_primary.vhd
sdram_control/sim/work/altfp_mult/verilog.asm
sdram_control/sim/work/altfp_mult/_primary.dat
sdram_control/sim/work/altfp_mult/_primary.vhd
sdram_control/sim/work/altlvds_rx/verilog.asm
sdram_control/sim/work/altlvds_rx/_primary.dat
sdram_control/sim/work/altlvds_rx/_primary.vhd
sdram_control/sim/work/altlvds_tx/verilog.asm
sdram_control/sim/work/altlvds_tx/_primary.dat
sdram_control/sim/work/altlvds_tx/_primary.vhd
sdram_control/sim/work/altmult_accum/verilog.asm
sdram_control/sim/work/altmult_accum/_primary.dat
sdram_control/sim/work/altmult_accum/_primary.vhd
sdram_control/sim/work/altmult_add/verilog.asm
sdram_control/sim/work/altmult_add/_primary.dat
sdram_control/sim/work/altmult_add/_primary.vhd
sdram_control/sim/work/altpll/verilog.asm
sdram_control/sim/work/altpll/_primary.dat
sdram_control/sim/work/altpll/_primary.vhd
sdram_control/sim/work/altqpram/verilog.asm
sdram_control/sim/work/altqpram/_primary.dat
sdram_control/sim/work/altqpram/_primary.vhd
sdram_control/sim/work/altshift_taps/verilog.asm
sdram_control/sim/work/altshift_taps/_primary.dat
sdram_control/sim/work/altshift_taps/_primary.vhd
sdram_control/sim/work/altsqrt/verilog.asm
sdram_control/sim/work/altsqrt/_primary.dat
sdram_control/sim/work/altsqrt/_primary.vhd
sdram_control/sim/work/altsyncram/verilog.asm
sdram_control/sim/work/altsyncram/_primary.dat
sdram_control/sim/work/altsyncram/_primary.vhd
sdram_control/sim/work/alt_exc_dpram/verilog.asm
sdram_control/sim/work/alt_exc_dpram/_primary.dat
sdram_control/sim/work/alt_exc_dpram/_primary.vhd
sdram_control/sim/work/alt_exc_upcore/verilog.asm
sdram_control/sim/work/alt_exc_upcore/_primary.dat
sdram_control/sim/work/alt_exc_upcore/_primary.vhd
sdram_control/sim/work/arm_m_cntr/verilog.asm
sdram_control/sim/work/arm_m_cntr/_primary.dat
sdram_control/sim/work/arm_m_cntr/_primary.vhd
sdram_control/sim/work/arm_n_cntr/verilog.asm
sdram_control/sim/work/arm_n_cntr/_primary.dat
sdram_control/sim/work/arm_n_cntr/_primary.vhd
sdram_control/sim/work/arm_scale_cntr/verilog.asm
sdram_control/sim/work/arm_scale_cntr/_primary.dat
sdram_control/sim/work/arm_scale_cntr/_primary.vhd
sdram_control/sim/work/a_graycounter/verilog.asm
s
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