文件名称:code-led
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code seven leg
module bcd_tang (clock, rst, s1, led)
input clock, s1, rst
output [6:0] led
reg [6:0] led
reg [3:0] bcd
wire [3:0] bcd_next
always @(posedge clock or posedge rst)
begin
if (rst == 1 b1)
begin
bcd <= 4 b0
end
else if (s1 == 1 b1)
begin
bcd <= bcd_next // update new value
end
else
begin
bcd <= bcd // keep old value
end
end
assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1
// bcd : current stage
// bcd_next : next stage
always @(posedge clock)
begin
case(bcd)
4 b0000: led <= 7 b1111110
4 b0001: led <= 7 b0110000
4 b0010: led <= 7 b1101101
4 b0011: led <= 7 b1111001
4 b0100: led <= 7 b0110011
4 b0101: led <= 7 b1011011
4 b0110: led <= 7 b1011111
4 b0111: led <= 7 b1110000
4 b1000: led <= 7 b1111111
4 b1001: led <= 7 b1110011
default: led <= 7 b1111111
endcase
end
endmodule-code seven leg
module bcd_tang (clock, rst, s1, led)
input clock, s1, rst
output [6:0] led
reg [6:0] led
reg [3:0] bcd
wire [3:0] bcd_next
always @(posedge clock or posedge rst)
begin
if (rst == 1 b1)
begin
bcd <= 4 b0
end
else if (s1 == 1 b1)
begin
bcd <= bcd_next // update new value
end
else
begin
bcd <= bcd // keep old value
end
end
assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1
// bcd : current stage
// bcd_next : next stage
always @(posedge clock)
begin
case(bcd)
4 b0000: led <= 7 b1111110
4 b0001: led <= 7 b0110000
4 b0010: led <= 7 b1101101
4 b0011: led <= 7 b1111001
4 b0100: led <= 7 b0110011
4 b0101: led <= 7 b1011011
4 b0110: led <= 7 b1011111
4 b0111: led <= 7 b1110000
4 b1000: led <= 7 b1111111
4 b1001: led <= 7 b1110011
default: led <= 7 b1111111
endcase
end
endmodule
module bcd_tang (clock, rst, s1, led)
input clock, s1, rst
output [6:0] led
reg [6:0] led
reg [3:0] bcd
wire [3:0] bcd_next
always @(posedge clock or posedge rst)
begin
if (rst == 1 b1)
begin
bcd <= 4 b0
end
else if (s1 == 1 b1)
begin
bcd <= bcd_next // update new value
end
else
begin
bcd <= bcd // keep old value
end
end
assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1
// bcd : current stage
// bcd_next : next stage
always @(posedge clock)
begin
case(bcd)
4 b0000: led <= 7 b1111110
4 b0001: led <= 7 b0110000
4 b0010: led <= 7 b1101101
4 b0011: led <= 7 b1111001
4 b0100: led <= 7 b0110011
4 b0101: led <= 7 b1011011
4 b0110: led <= 7 b1011111
4 b0111: led <= 7 b1110000
4 b1000: led <= 7 b1111111
4 b1001: led <= 7 b1110011
default: led <= 7 b1111111
endcase
end
endmodule-code seven leg
module bcd_tang (clock, rst, s1, led)
input clock, s1, rst
output [6:0] led
reg [6:0] led
reg [3:0] bcd
wire [3:0] bcd_next
always @(posedge clock or posedge rst)
begin
if (rst == 1 b1)
begin
bcd <= 4 b0
end
else if (s1 == 1 b1)
begin
bcd <= bcd_next // update new value
end
else
begin
bcd <= bcd // keep old value
end
end
assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1
// bcd : current stage
// bcd_next : next stage
always @(posedge clock)
begin
case(bcd)
4 b0000: led <= 7 b1111110
4 b0001: led <= 7 b0110000
4 b0010: led <= 7 b1101101
4 b0011: led <= 7 b1111001
4 b0100: led <= 7 b0110011
4 b0101: led <= 7 b1011011
4 b0110: led <= 7 b1011111
4 b0111: led <= 7 b1110000
4 b1000: led <= 7 b1111111
4 b1001: led <= 7 b1110011
default: led <= 7 b1111111
endcase
end
endmodule
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