文件名称:LAB-2
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- 上传时间:2013-03-12
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文件大小:2.97mb
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用FPGA实现对VGA的控制,没有用到niosII,只是用硬件描述语言verilog。整个工程。-With FPGA VGA control is not used niosII, just verilog hardware descr iption language. The entire project.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LAB 2/colormap.v
LAB 2/db/altsyncram_0eq1.tdf
LAB 2/db/altsyncram_7ri2.tdf
LAB 2/db/altsyncram_i1l1.tdf
LAB 2/db/altsyncram_k4p3.tdf
LAB 2/db/cmpr_5vh.tdf
LAB 2/db/cntr_2ci.tdf
LAB 2/db/cntr_3sf.tdf
LAB 2/db/cntr_4jg.tdf
LAB 2/db/cntr_4qh.tdf
LAB 2/db/cntr_cai.tdf
LAB 2/db/cntr_dne.tdf
LAB 2/db/cntr_gui.tdf
LAB 2/db/cntr_p6j.tdf
LAB 2/db/cntr_qjf.tdf
LAB 2/db/decode_4oa.tdf
LAB 2/db/decode_aoi.tdf
LAB 2/db/decode_rqf.tdf
LAB 2/db/design.(0).cnf.cdb
LAB 2/db/design.(0).cnf.hdb
LAB 2/db/design.(1).cnf.cdb
LAB 2/db/design.(1).cnf.hdb
LAB 2/db/design.(2).cnf.cdb
LAB 2/db/design.(2).cnf.hdb
LAB 2/db/design.(3).cnf.cdb
LAB 2/db/design.(3).cnf.hdb
LAB 2/db/design.amm.cdb
LAB 2/db/design.asm.qmsg
LAB 2/db/design.asm.rdb
LAB 2/db/design.asm_labs.ddb
LAB 2/db/design.cbx.xml
LAB 2/db/design.cmp.bpm
LAB 2/db/design.cmp.cdb
LAB 2/db/design.cmp.hdb
LAB 2/db/design.cmp.kpt
LAB 2/db/design.cmp.logdb
LAB 2/db/design.cmp.rdb
LAB 2/db/design.cmp2.ddb
LAB 2/db/design.cmp_merge.kpt
LAB 2/db/design.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
LAB 2/db/design.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
LAB 2/db/design.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
LAB 2/db/design.db_info
LAB 2/db/design.fit.qmsg
LAB 2/db/design.hier_info
LAB 2/db/design.hif
LAB 2/db/design.idb.cdb
LAB 2/db/design.lpc.html
LAB 2/db/design.lpc.rdb
LAB 2/db/design.lpc.txt
LAB 2/db/design.map.bpm
LAB 2/db/design.map.cdb
LAB 2/db/design.map.hdb
LAB 2/db/design.map.kpt
LAB 2/db/design.map.logdb
LAB 2/db/design.map.qmsg
LAB 2/db/design.map_bb.cdb
LAB 2/db/design.map_bb.hdb
LAB 2/db/design.map_bb.logdb
LAB 2/db/design.pre_map.cdb
LAB 2/db/design.pre_map.hdb
LAB 2/db/design.root_partition.map.reg_db.cdb
LAB 2/db/design.rtlv.hdb
LAB 2/db/design.rtlv_sg.cdb
LAB 2/db/design.rtlv_sg_swap.cdb
LAB 2/db/design.sgdiff.cdb
LAB 2/db/design.sgdiff.hdb
LAB 2/db/design.sld_design_entry.sci
LAB 2/db/design.sld_design_entry_dsc.sci
LAB 2/db/design.smart_action.txt
LAB 2/db/design.sta.qmsg
LAB 2/db/design.sta.rdb
LAB 2/db/design.sta_cmp.7_slow_1200mv_85c.tdb
LAB 2/db/design.syn_hier_info
LAB 2/db/design.tiscmp.fast_1200mv_0c.ddb
LAB 2/db/design.tiscmp.slow_1200mv_0c.ddb
LAB 2/db/design.tiscmp.slow_1200mv_85c.ddb
LAB 2/db/design.tis_db_list.ddb
LAB 2/db/design.tmw_info
LAB 2/db/logic_util_heursitic.dat
LAB 2/db/mux_foc.tdf
LAB 2/db/mux_jib.tdf
LAB 2/db/prev_cmp_design.map.qmsg
LAB 2/db/prev_cmp_design.qmsg
LAB 2/db/wed.zsf
LAB 2/design.asm.rpt
LAB 2/design.bdf
LAB 2/design.cdf
LAB 2/design.done
LAB 2/design.fit.rpt
LAB 2/design.fit.smsg
LAB 2/design.fit.summary
LAB 2/design.flow.rpt
LAB 2/design.jdi
LAB 2/design.map.rpt
LAB 2/design.map.summary
LAB 2/design.pin
LAB 2/design.pof
LAB 2/design.qpf
LAB 2/design.qsf
LAB 2/design.qws
LAB 2/design.sof
LAB 2/design.sta.rpt
LAB 2/design.sta.summary
LAB 2/design.tan.rpt
LAB 2/design.tan.summary
LAB 2/design.vwf
LAB 2/design_assignment_defaults.qdf
LAB 2/incremental_db/compiled_partitions/design.db_info
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.dfp
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.kpt
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.logdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.rcfdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.dpi
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.hb_info
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.sig
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.kpt
LAB 2/incremental_db/README
LAB 2/vgacore.bsf
LAB 2/vgacore.v
LAB 2/vgasig.v
LAB 2/incremental_db/compiled_partitions
LAB 2/db
LAB 2/incremental_db
LAB 2
LAB 2/db/altsyncram_0eq1.tdf
LAB 2/db/altsyncram_7ri2.tdf
LAB 2/db/altsyncram_i1l1.tdf
LAB 2/db/altsyncram_k4p3.tdf
LAB 2/db/cmpr_5vh.tdf
LAB 2/db/cntr_2ci.tdf
LAB 2/db/cntr_3sf.tdf
LAB 2/db/cntr_4jg.tdf
LAB 2/db/cntr_4qh.tdf
LAB 2/db/cntr_cai.tdf
LAB 2/db/cntr_dne.tdf
LAB 2/db/cntr_gui.tdf
LAB 2/db/cntr_p6j.tdf
LAB 2/db/cntr_qjf.tdf
LAB 2/db/decode_4oa.tdf
LAB 2/db/decode_aoi.tdf
LAB 2/db/decode_rqf.tdf
LAB 2/db/design.(0).cnf.cdb
LAB 2/db/design.(0).cnf.hdb
LAB 2/db/design.(1).cnf.cdb
LAB 2/db/design.(1).cnf.hdb
LAB 2/db/design.(2).cnf.cdb
LAB 2/db/design.(2).cnf.hdb
LAB 2/db/design.(3).cnf.cdb
LAB 2/db/design.(3).cnf.hdb
LAB 2/db/design.amm.cdb
LAB 2/db/design.asm.qmsg
LAB 2/db/design.asm.rdb
LAB 2/db/design.asm_labs.ddb
LAB 2/db/design.cbx.xml
LAB 2/db/design.cmp.bpm
LAB 2/db/design.cmp.cdb
LAB 2/db/design.cmp.hdb
LAB 2/db/design.cmp.kpt
LAB 2/db/design.cmp.logdb
LAB 2/db/design.cmp.rdb
LAB 2/db/design.cmp2.ddb
LAB 2/db/design.cmp_merge.kpt
LAB 2/db/design.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
LAB 2/db/design.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
LAB 2/db/design.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
LAB 2/db/design.db_info
LAB 2/db/design.fit.qmsg
LAB 2/db/design.hier_info
LAB 2/db/design.hif
LAB 2/db/design.idb.cdb
LAB 2/db/design.lpc.html
LAB 2/db/design.lpc.rdb
LAB 2/db/design.lpc.txt
LAB 2/db/design.map.bpm
LAB 2/db/design.map.cdb
LAB 2/db/design.map.hdb
LAB 2/db/design.map.kpt
LAB 2/db/design.map.logdb
LAB 2/db/design.map.qmsg
LAB 2/db/design.map_bb.cdb
LAB 2/db/design.map_bb.hdb
LAB 2/db/design.map_bb.logdb
LAB 2/db/design.pre_map.cdb
LAB 2/db/design.pre_map.hdb
LAB 2/db/design.root_partition.map.reg_db.cdb
LAB 2/db/design.rtlv.hdb
LAB 2/db/design.rtlv_sg.cdb
LAB 2/db/design.rtlv_sg_swap.cdb
LAB 2/db/design.sgdiff.cdb
LAB 2/db/design.sgdiff.hdb
LAB 2/db/design.sld_design_entry.sci
LAB 2/db/design.sld_design_entry_dsc.sci
LAB 2/db/design.smart_action.txt
LAB 2/db/design.sta.qmsg
LAB 2/db/design.sta.rdb
LAB 2/db/design.sta_cmp.7_slow_1200mv_85c.tdb
LAB 2/db/design.syn_hier_info
LAB 2/db/design.tiscmp.fast_1200mv_0c.ddb
LAB 2/db/design.tiscmp.slow_1200mv_0c.ddb
LAB 2/db/design.tiscmp.slow_1200mv_85c.ddb
LAB 2/db/design.tis_db_list.ddb
LAB 2/db/design.tmw_info
LAB 2/db/logic_util_heursitic.dat
LAB 2/db/mux_foc.tdf
LAB 2/db/mux_jib.tdf
LAB 2/db/prev_cmp_design.map.qmsg
LAB 2/db/prev_cmp_design.qmsg
LAB 2/db/wed.zsf
LAB 2/design.asm.rpt
LAB 2/design.bdf
LAB 2/design.cdf
LAB 2/design.done
LAB 2/design.fit.rpt
LAB 2/design.fit.smsg
LAB 2/design.fit.summary
LAB 2/design.flow.rpt
LAB 2/design.jdi
LAB 2/design.map.rpt
LAB 2/design.map.summary
LAB 2/design.pin
LAB 2/design.pof
LAB 2/design.qpf
LAB 2/design.qsf
LAB 2/design.qws
LAB 2/design.sof
LAB 2/design.sta.rpt
LAB 2/design.sta.summary
LAB 2/design.tan.rpt
LAB 2/design.tan.summary
LAB 2/design.vwf
LAB 2/design_assignment_defaults.qdf
LAB 2/incremental_db/compiled_partitions/design.db_info
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.dfp
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.kpt
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.logdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.cmp.rcfdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.dpi
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.cdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.hb_info
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hbdb.sig
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.hdb
LAB 2/incremental_db/compiled_partitions/design.root_partition.map.kpt
LAB 2/incremental_db/README
LAB 2/vgacore.bsf
LAB 2/vgacore.v
LAB 2/vgasig.v
LAB 2/incremental_db/compiled_partitions
LAB 2/db
LAB 2/incremental_db
LAB 2
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