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文件名称:t48u_latest.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2013-03-16
  • 文件大小：
    4.01mb
  • 已下载：
    0次
  • 提 供 者：
    k***
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

The T48 μController core is an implementation of the MCS-48 microcontroller family ar-chitecture. While being a controller core for SoC, it also aims for code-compatability and

cycle-accuracy so that it can be used as a drop-in replacement for any MCS-48 controller.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

t48/
t48/tags/
t48/tags/rel_0_3_beta/
t48/tags/rel_0_3_beta/COMPILE_LIST
t48/tags/rel_0_3_beta/sim/
t48/tags/rel_0_3_beta/sim/rtl_sim/
t48/tags/rel_0_3_beta/sim/rtl_sim/Makefile.ghdl
t48/tags/rel_0_3_beta/sim/rtl_sim/Makefile.simili
t48/tags/rel_0_3_beta/sim/rtl_sim/Makefile.hier
t48/tags/rel_0_3_beta/README
t48/tags/rel_0_3_beta/KNOWN_BUGS
t48/tags/rel_0_3_beta/bench/
t48/tags/rel_0_3_beta/bench/vhdl/
t48/tags/rel_0_3_beta/bench/vhdl/tb.vhd
t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048-c.vhd
t48/tags/rel_0_3_beta/bench/vhdl/if_timing.vhd
t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
t48/tags/rel_0_3_beta/bench/vhdl/tb_t8039-c.vhd
t48/tags/rel_0_3_beta/bench/vhdl/tb_t8039.vhd
t48/tags/rel_0_3_beta/bench/vhdl/tb-c.vhd
t48/tags/rel_0_3_beta/bench/vhdl/if_timing-c.vhd
t48/tags/rel_0_3_beta/rtl/
t48/tags/rel_0_3_beta/rtl/vhdl/
t48/tags/rel_0_3_beta/rtl/vhdl/db_bus.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/alu.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_core.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_core-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/p1.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_tb_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/p2-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/p2.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/opc_decoder.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/
t48/tags/rel_0_3_beta/rtl/vhdl/system/lpm_rom.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/t8048-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_rom-lpm-a.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/t8048.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/lpm_ram_dq.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/t8039.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_rom-e.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_ram-e.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_rom-lpm-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/t8039-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_ram-lpm-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/system/syn_ram-lpm-a.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/decoder-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/clock_ctrl.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_comp_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/cond_branch-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/bus_mux.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/clock_ctrl-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/psw.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/opc_table-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/int-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/timer-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/pmem_ctrl.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/alu_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/bus_mux-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/decoder_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/alu-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/db_bus-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/int.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/opc_decoder-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/dmem_ctrl-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/cond_branch_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/dmem_ctrl_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/t48_core_comp_pack-p.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/opc_table.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/decoder.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/pmem_ctrl-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/p1-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/cond_branch.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/dmem_ctrl.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/psw-c.vhd
t48/tags/rel_0_3_beta/rtl/vhdl/pmem_ctrl_pack-p.vhd
t48/tags/rel_0_3_beta/sw/
t48/tags/rel_0_3_beta/sw/init_project.template.sh
t48/tags/rel_0_3_beta/sw/run_regression.pl
t48/tags/rel_0_3_beta/sw/verif/
t48/tags/rel_0_3_beta/sw/verif/include/
t48/tags/rel_0_3_beta/sw/verif/include/cpu.inc
t48/tags/rel_0_3_beta/sw/verif/include/Makefile.cell
t48/tags/rel_0_3_beta/sw/verif/include/pass_fail.inc
t48/tags/rel_0_3_beta/sw/verif/include/Makefile.core
t48/tags/rel_0_3_beta/sw/verif/gp_sw/
t48/tags/rel_0_3_beta/sw/verif/gp_sw/toggle/
t48/tags/rel_0_3_beta/sw/verif/gp_sw/toggle/test.asm
t48/tags/rel_0_3_beta/sw/verif/white_box/
t48/tags/rel_0_3_beta/sw/verif/white_box/p2_port_reg_conflict/
t48/tags/rel_0_3_beta/sw/verif/white_box/p2_port_reg_conflict/no_dump_compare
t48/tags/rel_0_3_beta/sw/verif/white_box/p2_port_reg_conflict/test.asm
t48/tags/rel_0_3_beta/sw/verif/white_box/p1_port_reg_conflict/
t48/tags/rel_0_3_beta/sw/verif/white_box/p1_port_reg_conflict/no_dump_compare
t48/tags/rel_0_3_beta/sw/verif/white_box/p1_port_reg_conflict/test.asm
t48/tags/rel_0_3_beta/sw/verif/black_box/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/ind_rr/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/ind_rr/test.asm
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/a_rr/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/a_rr/data_num/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/a_rr/data_num/test.asm
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/a_rr/data_00/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/a_rr/data_00/test.asm
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/mov_rr_a/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/mov_rr_a/data_num/
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm
t48/tags/rel_0_3_beta/sw/verif/black_box/mov/mov_rr_a/data_00/
t48/tags/rel_

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