文件名称:div5
介绍说明--下载内容来自于网络,使用问题请自行百度
用verilog描述的任意分频器,包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
div5/designer/impl1/designer_genhdl.log
div5/designer/impl1/div.tcl
div5/div5.prj
div5/hdl/div5.v
div5/hdl/waveperl.log
div5/simulation/modelsim.ini
div5/simulation/modelsim.ini.sav
div5/simulation/modelsim.log
div5/simulation/postsynth/div/verilog.psm
div5/simulation/postsynth/div/_primary.dat
div5/simulation/postsynth/div/_primary.dbs
div5/simulation/postsynth/div/_primary.vhd
div5/simulation/postsynth/_info
div5/simulation/presynth/div/verilog.psm
div5/simulation/presynth/div/_primary.dat
div5/simulation/presynth/div/_primary.dbs
div5/simulation/presynth/div/_primary.vhd
div5/simulation/presynth/_info
div5/simulation/run.do
div5/simulation/vsim.wlf
div5/simulation/work/div/verilog.psm
div5/simulation/work/div/_primary.dat
div5/simulation/work/div/_primary.dbs
div5/simulation/work/div/_primary.vhd
div5/simulation/work/_info
div5/smartgen/smartgen.aws
div5/synthesis/div.areasrr
div5/synthesis/div.edn
div5/synthesis/div.fse
div5/synthesis/div.htm
div5/synthesis/div.map
div5/synthesis/div.sap
div5/synthesis/div.sdf
div5/synthesis/div.so
div5/synthesis/div.srd
div5/synthesis/div.srm
div5/synthesis/div.srr
div5/synthesis/div.srs
div5/synthesis/div.tlg
div5/synthesis/div.v
div5/synthesis/div_sdc.sdc
div5/synthesis/div_syn.prj
div5/synthesis/run_options.txt
div5/synthesis/stdout.log
div5/synthesis/syntmp/div.msg
div5/synthesis/syntmp/div.plg
div5/synthesis/syntmp/div_flink.htm
div5/synthesis/syntmp/div_srr.htm
div5/synthesis/syntmp/div_toc.htm
div5/synthesis/syntmp/sap.log
div5/viewdraw/vf/project.lst
div5/viewdraw/viewdraw.ini
div5/designer/impl1/simulation
div5/simulation/postsynth/div
div5/simulation/postsynth/_temp
div5/simulation/presynth/div
div5/simulation/presynth/_temp
div5/simulation/work/div
div5/simulation/work/_temp
div5/designer/impl1
div5/simulation/postsynth
div5/simulation/presynth
div5/simulation/work
div5/synthesis/backup
div5/synthesis/syntmp
div5/viewdraw/sch
div5/viewdraw/sym
div5/viewdraw/vf
div5/viewdraw/wir
div5/component
div5/constraint
div5/coreconsole
div5/designer
div5/hdl
div5/phy_synthesis
div5/simulation
div5/smartgen
div5/stimulus
div5/synthesis
div5/viewdraw
div5
div5/designer/impl1/div.tcl
div5/div5.prj
div5/hdl/div5.v
div5/hdl/waveperl.log
div5/simulation/modelsim.ini
div5/simulation/modelsim.ini.sav
div5/simulation/modelsim.log
div5/simulation/postsynth/div/verilog.psm
div5/simulation/postsynth/div/_primary.dat
div5/simulation/postsynth/div/_primary.dbs
div5/simulation/postsynth/div/_primary.vhd
div5/simulation/postsynth/_info
div5/simulation/presynth/div/verilog.psm
div5/simulation/presynth/div/_primary.dat
div5/simulation/presynth/div/_primary.dbs
div5/simulation/presynth/div/_primary.vhd
div5/simulation/presynth/_info
div5/simulation/run.do
div5/simulation/vsim.wlf
div5/simulation/work/div/verilog.psm
div5/simulation/work/div/_primary.dat
div5/simulation/work/div/_primary.dbs
div5/simulation/work/div/_primary.vhd
div5/simulation/work/_info
div5/smartgen/smartgen.aws
div5/synthesis/div.areasrr
div5/synthesis/div.edn
div5/synthesis/div.fse
div5/synthesis/div.htm
div5/synthesis/div.map
div5/synthesis/div.sap
div5/synthesis/div.sdf
div5/synthesis/div.so
div5/synthesis/div.srd
div5/synthesis/div.srm
div5/synthesis/div.srr
div5/synthesis/div.srs
div5/synthesis/div.tlg
div5/synthesis/div.v
div5/synthesis/div_sdc.sdc
div5/synthesis/div_syn.prj
div5/synthesis/run_options.txt
div5/synthesis/stdout.log
div5/synthesis/syntmp/div.msg
div5/synthesis/syntmp/div.plg
div5/synthesis/syntmp/div_flink.htm
div5/synthesis/syntmp/div_srr.htm
div5/synthesis/syntmp/div_toc.htm
div5/synthesis/syntmp/sap.log
div5/viewdraw/vf/project.lst
div5/viewdraw/viewdraw.ini
div5/designer/impl1/simulation
div5/simulation/postsynth/div
div5/simulation/postsynth/_temp
div5/simulation/presynth/div
div5/simulation/presynth/_temp
div5/simulation/work/div
div5/simulation/work/_temp
div5/designer/impl1
div5/simulation/postsynth
div5/simulation/presynth
div5/simulation/work
div5/synthesis/backup
div5/synthesis/syntmp
div5/viewdraw/sch
div5/viewdraw/sym
div5/viewdraw/vf
div5/viewdraw/wir
div5/component
div5/constraint
div5/coreconsole
div5/designer
div5/hdl
div5/phy_synthesis
div5/simulation
div5/smartgen
div5/stimulus
div5/synthesis
div5/viewdraw
div5
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