lab28-他人/
lab28-他人/ISE/
lab28-他人/ISE/DataRAM.asy
lab28-他人/ISE/DataRAM.ngc
lab28-他人/ISE/DataRAM.sym
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lab28-他人/ISE/DataRAM.veo
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lab28-他人/ISE/DataRAM.vho
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lab28-他人/ISE/DataRAM_readme.txt
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lab28-他人/ISE/mipspipelinecpu.bgn
lab28-他人/ISE/mipspipelinecpu.bit
lab28-他人/ISE/MipsPipelineCPU.bld
lab28-他人/ISE/MipsPipelineCPU.cel
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lab28-他人/ISE/mipspipelinecpu.drc
lab28-他人/ISE/MipsPipelineCPU.ise
lab28-他人/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/ISE/MipsPipelineCPU.lso
lab28-他人/ISE/MipsPipelineCPU.ncd
lab28-他人/ISE/MipsPipelineCPU.ngc
lab28-他人/ISE/MipsPipelineCPU.ngd
lab28-他人/ISE/MipsPipelineCPU.ngr
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lab28-他人/ISE/MipsPipelineCPU.pad
lab28-他人/ISE/MipsPipelineCPU.par
lab28-他人/ISE/MipsPipelineCPU.pcf
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lab28-他人/ISE/MipsPipelineCPU.ucf
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lab28-他人/ISE/MipsPipelineCPU.xpi
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lab28-他人/ISE/MipsPipelineCPU_map.map
lab28-他人/ISE/MipsPipelineCPU_map.mrp
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lab28-他人/ISE/MipsPipelineCPU_prev_built.ngd
lab28-他人/ISE/MipsPipelineCPU_summary.html
lab28-他人/ISE/MipsPipelineCPU_summary.xml
lab28-他人/ISE/MipsPipelineCPU_usage.xml
lab28-他人/ISE/templates/
lab28-他人/ISE/templates/coregen.xml
lab28-他人/ISE/tmp/
lab28-他人/ISE/tmp/_cg/
lab28-他人/ISE/transcript
lab28-他人/ISE/xst/
lab28-他人/ISE/xst/dump.xst/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/notopt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/opt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ntrc.scr
lab28-他人/ISE/xst/projnav.tmp/
lab28-他人/ISE/xst/work/
lab28-他人/ISE/xst/work/hdllib.ref
lab28-他人/ISE/xst/work/vlg0E/
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lab28-他人/ISE/xst/work/vlg1E/
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lab28-他人/ISE/xst/work/vlg1F/
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lab28-他人/ISE/xst/work/vlg27/
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lab28-他人/ISE/xst/work/vlg2A/
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lab28-他人/ISE/xst/work/vlg2F/
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lab28-他人/ISE/xst/work/vlg30/
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lab28-他人/ISE/xst/work/vlg31/
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lab28-他人/ISE/xst/work/vlg33/
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lab28-他人/ISE/xst/work/vlg54/
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lab28-他人/ISE/xst/work/vlg66/
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lab28-他人/ISE/xst/work/vlg6D/
lab28-他人/ISE/xst/work/vlg6D/_d___f_f_r.bin
lab28-他人/ISE/xst/work/vlg73/
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lab28-他人/ISE/xst/work/vlg7C/
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lab28-他人/ISE/_impact.cmd
lab28-他人/ISE/_impact.log
lab28-他人/ISE/_ngo/
lab28-他人/ISE/_ngo/netlist.lst
lab28-他人/ISE/_xmsgs/
lab28-他人/ISE/_xmsgs/bitgen.xmsgs
lab28-他人/ISE/_xmsgs/map.xmsgs
lab28-他人/ISE/_xmsgs/ngdbuild.xmsgs
lab28-他人/ISE/_xmsgs/par.xmsgs
lab28-他人/ISE/_xmsgs/trce.xmsgs
lab28-他人/ISE/_xmsgs/xst.xmsgs
lab28-他人/PipelineCPU/
lab28-他人/PipelineCPU/ISE/
lab28-他人/PipelineCPU/ISE/DataRAM.asy
lab28-他人/PipelineCPU/ISE/DataRAM.ngc
lab28-他人/PipelineCPU/ISE/DataRAM.sym
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lab28-他人/PipelineCPU/ISE/DataRAM_flist.txt
lab28-他人/PipelineCPU/ISE/DataRAM_readme.txt
lab28-他人/PipelineCPU/ISE/DataRAM_xmdf.tcl
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.restore
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU_summary.html
lab28-他人/PipelineCPU/ISE/templates/
lab28-他人/PipelineCPU/ISE/templates/coregen.xml
lab28-他人/PipelineCPU/ISE/tmp/
lab28-他人/PipelineCPU/ISE/tmp/_cg/
lab28-他人/PipelineCPU/ISE/_xmsgs/
lab28-他人/PipelineCPU/SIM/
lab28-他人/PipelineCPU/SIM/ALU/
lab28-他人/PipelineCPU/SIM/ALU/adder.v
lab28-他人/PipelineCPU/SIM/ALU/adder_32bits.v
lab28-他人/PipelineCPU/SIM/ALU/ALU.cr.mti
lab28-他人/PipelineCPU/SIM/ALU/ALU.mpf
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lab28-他人/PipelineCPU/SIM/ALU/ALU.v.bak
lab28-他人/PipelineCPU/SIM/ALU/ALU_tb.v
lab28-他人/PipelineCPU/SIM/ALU/mux_2to1.v
lab28-他人/PipelineCPU/SIM/ALU/transcript
lab28-他人/PipelineCPU/SIM/ALU/vsim.wlf
lab28-他人/PipelineCPU/SIM/ALU/work/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.asm
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.rw
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lab28-他人/Pipel