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文件名称:EP2C8-2010_FPGA

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    2013-08-20
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EP2C208C8 FPGA开发源代码(芯蓝C8板)

turn_on_led  

  点亮LED

sw_led

  拨动开关控制LED

rider_led

  跑马灯

water_led

  流水灯

key_led_without_debounce

  轻触开关控制LED,无按键去抖

key_led_with_debounce

  轻触开关控制LED,有按键去抖

seg7x8_dynamic_disp

  七段数码管动态显示



matrixKeyboard_seg7

  测试矩阵键盘,七段数码管显示

beep_test

  滴滴声,测试蜂鸣器

beep_matrixKeyboard

  简易不同频率发声器

lcd1602_test

  测试LCD1602显示

lcd1602_clock

  简易时钟,LCD1602显示

vga_color_slip

  VGA显示彩条

vga_char

  VGA显示字符

uart_tx_test

  串口发送测试

uart_rx_test

  串口接收测试

ps2_keyboard_test

  PS2键盘测试,LCD1602显示-# Copyright (C) 1991-2009 Altera Corporation

# Your use of Altera Corporation s design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscr iption Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

--------------------------------------------------------------------------#

#

# Quartus II

# Version 9.0 Build 132 02/25/2009 SJ Full Version

# Date created = 09:05:11 March 14, 2010

#

#--------------
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA
FPGA/EP2C8-2010管脚索引.txt
FPGA/_10_beep_matrixKeyboard
FPGA/_10_beep_matrixKeyboard/beep_test.done
FPGA/_10_beep_matrixKeyboard/beep_test.fit.smsg
FPGA/_10_beep_matrixKeyboard/beep_test.fit.summary
FPGA/_10_beep_matrixKeyboard/beep_test.map.summary
FPGA/_10_beep_matrixKeyboard/beep_test.pin
FPGA/_10_beep_matrixKeyboard/beep_test.pof
FPGA/_10_beep_matrixKeyboard/beep_test.qpf
FPGA/_10_beep_matrixKeyboard/beep_test.qsf
FPGA/_10_beep_matrixKeyboard/beep_test.qws
FPGA/_10_beep_matrixKeyboard/beep_test.sof
FPGA/_10_beep_matrixKeyboard/beep_test.tan.summary
FPGA/_10_beep_matrixKeyboard/beep_test_assignment_defaults.qdf
FPGA/_10_beep_matrixKeyboard/src
FPGA/_10_beep_matrixKeyboard/src/2C8 管脚.txt
FPGA/_10_beep_matrixKeyboard/src/BEEP 原理图.png
FPGA/_10_beep_matrixKeyboard/src/beep_test.v
FPGA/_10_beep_matrixKeyboard/src/matrixKeyboard_drive.v
FPGA/_10_beep_matrixKeyboard/src/音调的频率表.gif
FPGA/_11_lcd1602_test
FPGA/_11_lcd1602_test/db
FPGA/_11_lcd1602_test/db/lcd1602_test.db_info
FPGA/_11_lcd1602_test/db/lcd1602_test.eco.cdb
FPGA/_11_lcd1602_test/db/lcd1602_test.sld_design_entry.sci
FPGA/_11_lcd1602_test/lcd1602_test.done
FPGA/_11_lcd1602_test/lcd1602_test.dpf
FPGA/_11_lcd1602_test/lcd1602_test.fit.smsg
FPGA/_11_lcd1602_test/lcd1602_test.fit.summary
FPGA/_11_lcd1602_test/lcd1602_test.map.summary
FPGA/_11_lcd1602_test/lcd1602_test.pin
FPGA/_11_lcd1602_test/lcd1602_test.pof
FPGA/_11_lcd1602_test/lcd1602_test.qpf
FPGA/_11_lcd1602_test/lcd1602_test.qsf
FPGA/_11_lcd1602_test/lcd1602_test.qws
FPGA/_11_lcd1602_test/lcd1602_test.sof
FPGA/_11_lcd1602_test/lcd1602_test.tan.summary
FPGA/_11_lcd1602_test/lcd1602_test_assignment_defaults.qdf
FPGA/_11_lcd1602_test/src
FPGA/_11_lcd1602_test/src/.xhdl3.xref
FPGA/_11_lcd1602_test/src/2C8 管脚.txt
FPGA/_11_lcd1602_test/src/LCD1602 原理图.png
FPGA/_11_lcd1602_test/src/LCD1602 状态机.jpg
FPGA/_11_lcd1602_test/src/lcd1602_drive.v
FPGA/_11_lcd1602_test/src/lcd1602_test.v
FPGA/_11_lcd1602_test/src/row1_val和row2_val中字符地址.png
FPGA/_12_lcd1602_clock
FPGA/_12_lcd1602_clock/db
FPGA/_12_lcd1602_clock/db/lcd1602_clock.db_info
FPGA/_12_lcd1602_clock/db/lcd1602_clock.eco.cdb
FPGA/_12_lcd1602_clock/db/lcd1602_clock.sld_design_entry.sci
FPGA/_12_lcd1602_clock/incremental_db
FPGA/_12_lcd1602_clock/incremental_db/compiled_partitions
FPGA/_12_lcd1602_clock/incremental_db/README
FPGA/_12_lcd1602_clock/lcd1602_clock.done
FPGA/_12_lcd1602_clock/lcd1602_clock.fit.smsg
FPGA/_12_lcd1602_clock/lcd1602_clock.fit.summary
FPGA/_12_lcd1602_clock/lcd1602_clock.map.smsg
FPGA/_12_lcd1602_clock/lcd1602_clock.map.summary
FPGA/_12_lcd1602_clock/lcd1602_clock.pin
FPGA/_12_lcd1602_clock/lcd1602_clock.pof
FPGA/_12_lcd1602_clock/lcd1602_clock.qpf
FPGA/_12_lcd1602_clock/lcd1602_clock.qsf
FPGA/_12_lcd1602_clock/lcd1602_clock.qws
FPGA/_12_lcd1602_clock/lcd1602_clock.sof
FPGA/_12_lcd1602_clock/lcd1602_clock.tan.summary
FPGA/_12_lcd1602_clock/lcd1602_clock_assignment_defaults.qdf
FPGA/_12_lcd1602_clock/src
FPGA/_12_lcd1602_clock/src/2C8 管脚.txt
FPGA/_12_lcd1602_clock/src/ASCII码表.png
FPGA/_12_lcd1602_clock/src/div_50M.v
FPGA/_12_lcd1602_clock/src/LCD1602 原理图.png
FPGA/_12_lcd1602_clock/src/LCD1602 状态机.jpg
FPGA/_12_lcd1602_clock/src/lcd1602_clock.v
FPGA/_12_lcd1602_clock/src/lcd1602_drive.v
FPGA/_12_lcd1602_clock/src/row1_val和row2_val中字符地址.png
FPGA/_13_vga_color_slip
FPGA/_13_vga_color_slip/640x480_60_25M
FPGA/_13_vga_color_slip/640x480_60_25M/src
FPGA/_13_vga_color_slip/640x480_60_25M/src/2C8 管脚.txt
FPGA/_13_vga_color_slip/640x480_60_25M/src/640x480@60.png
FPGA/_13_vga_color_slip/640x480_60_25M/src/disp_color_slip.v
FPGA/_13_vga_color_slip/640x480_60_25M/src/pll_CLOCK_25.ppf
FPGA/_13_vga_color_slip/640x480_60_25M/src/pll_CLOCK_25.qip
FPGA/_13_vga_color_slip/640x480_60_25M/src/pll_CLOCK_25.v
FPGA/_13_vga_color_slip/640x480_60_25M/src/VGA Signal Timing.url
FPGA/_13_vga_color_slip/640x480_60_25M/src/VGA 原理图.png
FPGA/_13_vga_color_slip/640x480_60_25M/src/vga_drive.v
FPGA/_13_vga_color_slip/640x480_60_25M/src/vga_test.v
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.done
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.fit.smsg
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.fit.summary
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.map.summary
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.pin
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.pof
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.qpf
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.qsf
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.qws
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.sof
FPGA/_13_vga_color_slip/640x480_60_25M/vga_test.tan.summary
FPGA/_13_vga_color_slip/800x600_72_50M
FPGA/_13_vga_color_slip/800x600_72_50M/src
FPGA/_13_vga_color_slip/800x600_72_50M/src/2C8 管脚.txt
FPGA/_13_vga_color_slip/800x600_72_50M/src/800x600@72.png
FPGA/_13_vga_color_slip/800x600_72_50M/src/disp_color_slip.v
FPGA/_13_vga_color_slip/800x600_72_50M/src/VGA Signal Timing.url
FPGA/_13_vga_color_slip/800x600_72_50M/src/VGA 原理图.png
FPGA/_13_vga_color_slip/800x600_72_50M/src/vga_drive.v
FPGA/_13_vga_color_slip/800x600_72_50M/src/vga_test.v
FPGA/_13_vga_color_slip/800x600_72_50M/vga_test.done
FPGA/_13_vga_color_slip/8

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