文件名称:SPI-Core_nguyen
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- 上传时间：2014-04-16
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文件大小：17.5kb
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已下载：1次
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SPI Master Core
HDL: VHDL 93
Compatibility: all FPGAs, CPLDs
parameterization:
- variable data width
- Phase/polarity configurable
- selectable buffer depth
- serial clock devision due to system clock
package usage:
IEEE.STD_LOGIC_1164
IEEE.NUMERIC_STD
work.general_signal_processing_pkg (included)
Testbench for simulation included.
Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
HDL: VHDL 93
Compatibility: all FPGAs, CPLDs
parameterization:
- variable data width
- Phase/polarity configurable
- selectable buffer depth
- serial clock devision due to system clock
package usage:
IEEE.STD_LOGIC_1164
IEEE.NUMERIC_STD
work.general_signal_processing_pkg (included)
Testbench for simulation included.
Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SPI Core_nguyen/general_signal_processing_pkg.vhd
SPI Core_nguyen/readme.txt
SPI Core_nguyen/spi_master_rev.vhd
SPI Core_nguyen/spi_master_rev_TB.vhd
SPI Core_nguyen/readme.txt
SPI Core_nguyen/spi_master_rev.vhd
SPI Core_nguyen/spi_master_rev_TB.vhd
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