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文件名称:Quartus_FPGA

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2014-04-21
  • 文件大小：
    151.16kb
  • 已下载：
    0次
  • 提 供 者：
    tak****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

this a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements-this is a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Quartus_FPGA/cod_priority.vhd
Quartus_FPGA/conv_bin_gray.asm.rpt
Quartus_FPGA/conv_bin_gray.done
Quartus_FPGA/conv_bin_gray.eda.rpt
Quartus_FPGA/conv_bin_gray.fit.rpt
Quartus_FPGA/conv_bin_gray.fit.smsg
Quartus_FPGA/conv_bin_gray.fit.summary
Quartus_FPGA/conv_bin_gray.flow.rpt
Quartus_FPGA/conv_bin_gray.map.rpt
Quartus_FPGA/conv_bin_gray.map.summary
Quartus_FPGA/conv_bin_gray.pin
Quartus_FPGA/conv_bin_gray.qpf
Quartus_FPGA/conv_bin_gray.qsf
Quartus_FPGA/conv_bin_gray.tan.rpt
Quartus_FPGA/conv_bin_gray.tan.summary
Quartus_FPGA/conv_bin_gray.vhd
Quartus_FPGA/conv_bin_gray.vhd.bak
Quartus_FPGA/conv_bin_gray_nativelink_simulation.rpt
Quartus_FPGA/Copie de DE2_pin_assignments.xlsx
Quartus_FPGA/db/conv_bin_gray.(0).cnf.cdb
Quartus_FPGA/db/conv_bin_gray.(0).cnf.hdb
Quartus_FPGA/db/conv_bin_gray.amm.cdb
Quartus_FPGA/db/conv_bin_gray.asm.qmsg
Quartus_FPGA/db/conv_bin_gray.cbx.xml
Quartus_FPGA/db/conv_bin_gray.cmp.bpm
Quartus_FPGA/db/conv_bin_gray.cmp.cbp
Quartus_FPGA/db/conv_bin_gray.cmp.cdb
Quartus_FPGA/db/conv_bin_gray.cmp.hdb
Quartus_FPGA/db/conv_bin_gray.cmp.kpt
Quartus_FPGA/db/conv_bin_gray.cmp.logdb
Quartus_FPGA/db/conv_bin_gray.cmp.tdb
Quartus_FPGA/db/conv_bin_gray.cmp_merge.kpt
Quartus_FPGA/db/conv_bin_gray.db_info
Quartus_FPGA/db/conv_bin_gray.eda.qmsg
Quartus_FPGA/db/conv_bin_gray.fit.qmsg
Quartus_FPGA/db/conv_bin_gray.hier_info
Quartus_FPGA/db/conv_bin_gray.hif
Quartus_FPGA/db/conv_bin_gray.idb.cdb
Quartus_FPGA/db/conv_bin_gray.lpc.html
Quartus_FPGA/db/conv_bin_gray.lpc.txt
Quartus_FPGA/db/conv_bin_gray.map.bpm
Quartus_FPGA/db/conv_bin_gray.map.cdb
Quartus_FPGA/db/conv_bin_gray.map.hdb
Quartus_FPGA/db/conv_bin_gray.map.kpt
Quartus_FPGA/db/conv_bin_gray.map.logdb
Quartus_FPGA/db/conv_bin_gray.map.qmsg
Quartus_FPGA/db/conv_bin_gray.map_bb.cdb
Quartus_FPGA/db/conv_bin_gray.map_bb.hdb
Quartus_FPGA/db/conv_bin_gray.map_bb.logdb
Quartus_FPGA/db/conv_bin_gray.pre_map.cdb
Quartus_FPGA/db/conv_bin_gray.pre_map.hdb
Quartus_FPGA/dec3_8.vhd
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.db_info
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.cdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.dfp
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.hdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.kpt
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.logdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.rcfdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.cmp.re.rcfdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.map.cdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.map.dpi
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.map.hdb
Quartus_FPGA/incremental_db/compiled_partitions/conv_bin_gray.root_partition.map.kpt
Quartus_FPGA/incremental_db/README
Quartus_FPGA/simulation/modelsim/conv_bin_gray.sft
Quartus_FPGA/simulation/modelsim/conv_bin_gray.vho
Quartus_FPGA/simulation/modelsim/conv_bin_gray_modelsim.xrf
Quartus_FPGA/simulation/modelsim/conv_bin_gray_run_msim_rtl_vhdl.do
Quartus_FPGA/simulation/modelsim/conv_bin_gray_run_msim_rtl_vhdl.do.bak
Quartus_FPGA/simulation/modelsim/conv_bin_gray_run_msim_rtl_vhdl.do.bak1
Quartus_FPGA/simulation/modelsim/conv_bin_gray_vhd.sdo
Quartus_FPGA/simulation/modelsim/msim_transcript
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/whenelse.dat
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/whenelse.dbs
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/whenelse.prw
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/whenelse.psm
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/_primary.dat
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8/_primary.dbs
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/test.dat
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/test.dbs
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/test.prw
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/test.psm
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/_primary.dat
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority/_primary.dbs
Quartus_FPGA/simulation/modelsim/rtl_work/_info
Quartus_FPGA/simulation/modelsim/rtl_work/_vmake
Quartus_FPGA/simulation/modelsim/vsim.wlf
Quartus_FPGA/tb_cod_priority.vhd
Quartus_FPGA/tb_dec3_8.vhd
Quartus_FPGA/simulation/modelsim/rtl_work/dec3_8
Quartus_FPGA/simulation/modelsim/rtl_work/tb_cod_priority
Quartus_FPGA/simulation/modelsim/rtl_work/_temp
Quartus_FPGA/simulation/modelsim/rtl_work
Quartus_FPGA/incremental_db/compiled_partitions
Quartus_FPGA/simulation/modelsim
Quartus_FPGA/db
Quartus_FPGA/incremental_db
Quartus_FPGA/simulation
Quartus_FPGA

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