文件名称:OpenMIPS_VerilogHDL_Study_v1.1
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- 上传时间：2014-05-02
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文件大小：430.4kb
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10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
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下载文件列表
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc/data_ram.v
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc/inst_rom.v
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc/openmips_min_sopc.v
OpenMIPS_VerilogHDL_Study_v1.1/openmips模块连接关系图.vsd
OpenMIPS_VerilogHDL_Study_v1.1/rtl/cp0_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ctrl.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/defines.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/div.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ex.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ex_mem.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/hilo_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/id.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/id_ex.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/if_id.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/LLbit_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/mem.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/mem_wb.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/openmips.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/pc_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/regfile.v
OpenMIPS_VerilogHDL_Study_v1.1/testbench/openmips_min_sopc_tb.v
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc
OpenMIPS_VerilogHDL_Study_v1.1/rtl
OpenMIPS_VerilogHDL_Study_v1.1/testbench
OpenMIPS_VerilogHDL_Study_v1.1
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc/inst_rom.v
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc/openmips_min_sopc.v
OpenMIPS_VerilogHDL_Study_v1.1/openmips模块连接关系图.vsd
OpenMIPS_VerilogHDL_Study_v1.1/rtl/cp0_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ctrl.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/defines.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/div.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ex.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/ex_mem.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/hilo_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/id.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/id_ex.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/if_id.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/LLbit_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/mem.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/mem_wb.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/openmips.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/pc_reg.v
OpenMIPS_VerilogHDL_Study_v1.1/rtl/regfile.v
OpenMIPS_VerilogHDL_Study_v1.1/testbench/openmips_min_sopc_tb.v
OpenMIPS_VerilogHDL_Study_v1.1/min_sopc
OpenMIPS_VerilogHDL_Study_v1.1/rtl
OpenMIPS_VerilogHDL_Study_v1.1/testbench
OpenMIPS_VerilogHDL_Study_v1.1
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