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文件名称:FPGA_CRC

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-06-26
  • 文件大小：
    1.14mb
  • 已下载：
    1次
  • 提 供 者：
    yuant*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source code, and the principles of my hand calculations. This program has been ModelSim-Altera simulation, simulation waveform files are in this document.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA_CRC/CCITT.qpf
FPGA_CRC/CCITT.qsf
FPGA_CRC/CCITT.qws
FPGA_CRC/CCITT.v
FPGA_CRC/CCITT.v.bak
FPGA_CRC/CCITT_nativelink_simulation.rpt
FPGA_CRC/db/CCITT.(0).cnf.cdb
FPGA_CRC/db/CCITT.(0).cnf.hdb
FPGA_CRC/db/CCITT.asm.qmsg
FPGA_CRC/db/CCITT.asm.rdb
FPGA_CRC/db/CCITT.asm_labs.ddb
FPGA_CRC/db/CCITT.cbx.xml
FPGA_CRC/db/CCITT.cmp.cdb
FPGA_CRC/db/CCITT.cmp.hdb
FPGA_CRC/db/CCITT.cmp.idb
FPGA_CRC/db/CCITT.cmp.kpt
FPGA_CRC/db/CCITT.cmp.logdb
FPGA_CRC/db/CCITT.cmp.rdb
FPGA_CRC/db/CCITT.cmp0.ddb
FPGA_CRC/db/CCITT.cmp2.ddb
FPGA_CRC/db/CCITT.cmp_merge.kpt
FPGA_CRC/db/CCITT.db_info
FPGA_CRC/db/CCITT.eda.qmsg
FPGA_CRC/db/CCITT.fit.qmsg
FPGA_CRC/db/CCITT.hier_info
FPGA_CRC/db/CCITT.hif
FPGA_CRC/db/CCITT.ipinfo
FPGA_CRC/db/CCITT.lpc.html
FPGA_CRC/db/CCITT.lpc.rdb
FPGA_CRC/db/CCITT.lpc.txt
FPGA_CRC/db/CCITT.map.ammdb
FPGA_CRC/db/CCITT.map.cdb
FPGA_CRC/db/CCITT.map.hdb
FPGA_CRC/db/CCITT.map.kpt
FPGA_CRC/db/CCITT.map.logdb
FPGA_CRC/db/CCITT.map.qmsg
FPGA_CRC/db/CCITT.map.rdb
FPGA_CRC/db/CCITT.pre_map.hdb
FPGA_CRC/db/CCITT.pti_db_list.ddb
FPGA_CRC/db/CCITT.root_partition.map.reg_db.cdb
FPGA_CRC/db/CCITT.routing.rdb
FPGA_CRC/db/CCITT.rtlv.hdb
FPGA_CRC/db/CCITT.rtlv_sg.cdb
FPGA_CRC/db/CCITT.rtlv_sg_swap.cdb
FPGA_CRC/db/CCITT.sgdiff.cdb
FPGA_CRC/db/CCITT.sgdiff.hdb
FPGA_CRC/db/CCITT.sld_design_entry.sci
FPGA_CRC/db/CCITT.sld_design_entry_dsc.sci
FPGA_CRC/db/CCITT.smart_action.txt
FPGA_CRC/db/CCITT.sta.qmsg
FPGA_CRC/db/CCITT.sta.rdb
FPGA_CRC/db/CCITT.sta_cmp.5_slow.tdb
FPGA_CRC/db/CCITT.syn_hier_info
FPGA_CRC/db/CCITT.tis_db_list.ddb
FPGA_CRC/db/CCITT.vpr.ammdb
FPGA_CRC/db/logic_util_heursitic.dat
FPGA_CRC/db/prev_cmp_CCITT.qmsg
FPGA_CRC/incremental_db/compiled_partitions/CCITT.db_info
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.ammdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.cdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.dfp
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.hdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.kpt
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.logdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.cmp.rcfdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.cdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.dpi
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.hbdb.cdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.hbdb.hb_info
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.hbdb.hdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.hbdb.sig
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.hdb
FPGA_CRC/incremental_db/compiled_partitions/CCITT.root_partition.map.kpt
FPGA_CRC/incremental_db/README
FPGA_CRC/output_files/CCITT.asm.rpt
FPGA_CRC/output_files/CCITT.done
FPGA_CRC/output_files/CCITT.eda.rpt
FPGA_CRC/output_files/CCITT.fit.rpt
FPGA_CRC/output_files/CCITT.fit.smsg
FPGA_CRC/output_files/CCITT.fit.summary
FPGA_CRC/output_files/CCITT.flow.rpt
FPGA_CRC/output_files/CCITT.jdi
FPGA_CRC/output_files/CCITT.map.rpt
FPGA_CRC/output_files/CCITT.map.summary
FPGA_CRC/output_files/CCITT.pin
FPGA_CRC/output_files/CCITT.pof
FPGA_CRC/output_files/CCITT.sof
FPGA_CRC/output_files/CCITT.sta.rpt
FPGA_CRC/output_files/CCITT.sta.summary
FPGA_CRC/simulation/modelsim/CCITT.sft
FPGA_CRC/simulation/modelsim/CCITT.vo
FPGA_CRC/simulation/modelsim/CCITT.vt
FPGA_CRC/simulation/modelsim/CCITT_fast.vo
FPGA_CRC/simulation/modelsim/CCITT_modelsim.xrf
FPGA_CRC/simulation/modelsim/CCITT_run_msim_gate_verilog.do
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak1
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak10
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak11
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak2
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak3
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak4
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak5
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak6
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak7
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak8
FPGA_CRC/simulation/modelsim/CCITT_run_msim_rtl_verilog.do.bak9
FPGA_CRC/simulation/modelsim/CCITT_v.sdo
FPGA_CRC/simulation/modelsim/CCITT_v_fast.sdo
FPGA_CRC/simulation/modelsim/CRC.cr.mti
FPGA_CRC/simulation/modelsim/CRC.mpf
FPGA_CRC/simulation/modelsim/gate_work/@c@c@i@t@t/verilog.prw
FPGA_CRC/simulation/modelsim/gate_work/@c@c@i@t@t/verilog.psm
FPGA_CRC/simulation/modelsim/gate_work/@c@c@i@t@t/_primary.dat
FPGA_CRC/simulation/modelsim/gate_work/@c@c@i@t@t/_primary.dbs
FPGA_CRC/simulation/modelsim/gate_work/@c@c@i@t@t/_primary.vhd
FPGA_CRC/simulation/modelsim/gate_work/_info
FPGA_CRC/simulation/modelsim/gate_work/_vmake
FPGA_CRC/simulation/modelsim/modelsim.ini
FPGA_CRC/simulation/modelsim/msim_

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