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文件名称:PCIe_Lab(ALTERA-V5PCIe)

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-08-03
  • 文件大小：
    6.32mb
  • 已下载：
    1次
  • 提 供 者：
    微***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。

-Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PCIe_Lab/.qsys_edit/filters.xml
PCIe_Lab/.qsys_edit/preferences.xml
PCIe_Lab/altgx_reconfig.v
PCIe_Lab/c4gx_qsys/synthesis/c4gx_qsys.qip
PCIe_Lab/c4gx_qsys/synthesis/c4gx_qsys.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_mm_bridge.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_sc_fifo.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_irq_clock_crosser.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_arbitrator.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_master_agent.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_master_translator.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_slave_agent.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_slave_translator.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_width_adapter.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_pcie_hard_ip_reset_controller.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_pci_express.sdc
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_reset_controller.sdc
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_reset_controller.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_reset_synchronizer.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altpcie_hip_pipen1b.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altpcie_pipe_interface.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altpcie_pll_100_250.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altpcie_pll_125_250.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/altpcie_rs_serdes.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/byte_enable_generator.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_addr_router.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_addr_router_001.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_addr_router_002.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_cmd_xbar_demux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_cmd_xbar_demux_001.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_cmd_xbar_demux_002.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_cmd_xbar_mux_003.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_cmd_xbar_mux_004.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_dma_0.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_id_router.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_id_router_001.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_id_router_003.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_id_router_004.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_irq_mapper.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_onchip_memory_0.hex
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_onchip_memory_0.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_addr_router.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_altgx_internal.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_cmd_xbar_demux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_id_router.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_rsp_xbar_demux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_pcie_hard_ip_0_rsp_xbar_mux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_rsp_xbar_demux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_rsp_xbar_demux_003.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_rsp_xbar_mux.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/c4gx_qsys_rsp_xbar_mux_002.sv
PCIe_Lab/c4gx_qsys/synthesis/submodules/csr_block.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/descriptor_buffers.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/dispatcher.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/fifo_with_byteenables.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/MM_to_ST_Adapter.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/pciexp64_trans.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/pciexp_dcram.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/read_burst_control.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/read_master.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/read_signal_breakout.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/response_block.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/ST_to_MM_Adapter.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/write_burst_control.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/write_master.v
PCIe_Lab/c4gx_qsys/synthesis/submodules/write_signal_breakout.v
PCIe_Lab/c4gx_qsys.bsf
PCIe_Lab/c4gx_qsys.html
PCIe_Lab/c4gx_qsys.qsys
PCIe_Lab/c4gx_qsys.sopcinfo
PCIe_Lab/incremental_db/compiled_partitions/top.db_info
PCIe_Lab/incremental_db/compiled_partitions/top.root_partition.cmp.cdb
PCIe_Lab/incremental_db/compiled_partitions/top.root_partition.cmp.dfp
PCIe_Lab/incremental_db/compiled_partitions/top.root_partition.cmp.hdb
PCIe_Lab/incremental_db/compiled_partitions/top.root_partition.cmp.kpt
PCIe_L

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