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文件名称:ddr2_sdram_latest.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-09-13
  • 文件大小：
    3.41mb
  • 已下载：
    0次
  • 提 供 者：
    包**
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1.初始化-Sequenz的RAM

2. Automaic写Sequenz（写入16数据字每一个64位的RAM）

3.自动读Sequenz（从RAM读出的第一个数据字）-1. Init-Sequenz for the RAM

2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM)

3. Automatic Read-Sequenz (reads the first Dataword　the RAM)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ddr2_sdram/
ddr2_sdram/tags/
ddr2_sdram/branches/
ddr2_sdram/trunk/
ddr2_sdram/trunk/Testbench_DDR2/
ddr2_sdram/trunk/Testbench_DDR2/Write/
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_05_DataLSB.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_09_NopCMD.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_Speed_187ns.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_10_OK.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_03_WriteEnable.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_08_DataMSB.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_06_WriteCMD_ACK.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_01_Timing.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Testbench_Write.vhd
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_07_BurstDone.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_04_WriteCMD.JPG
ddr2_sdram/trunk/Testbench_DDR2/Write/Write_02_Reset.JPG
ddr2_sdram/trunk/Testbench_DDR2/Clock/
ddr2_sdram/trunk/Testbench_DDR2/Clock/Clock_04_Phase_Shift.JPG
ddr2_sdram/trunk/Testbench_DDR2/Clock/Testbench_DDR2_Core.vhd
ddr2_sdram/trunk/Testbench_DDR2/Clock/Clock_03_Period.JPG
ddr2_sdram/trunk/Testbench_DDR2/Clock/Clock_02_Reset.JPG
ddr2_sdram/trunk/Testbench_DDR2/Clock/Clock_01_Timing.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_09_DataMSB.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Testbench_Read.vhd
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_10_Read_Ready.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_04_ReadCMD.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_07_NopCMD.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_06_BurstDone.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_11_Read_OK.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_03_ReadEnable.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_08_DataValid.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_05_ReadCMD_ACK.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_01_Timing.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_12_Read_Speed_165ns.JPG
ddr2_sdram/trunk/Testbench_DDR2/Read/Read_02_Reset.JPG
ddr2_sdram/trunk/DDR2_readme.txt
ddr2_sdram/trunk/Top_Modul_VHDL_summary.html
ddr2_sdram/trunk/Top_Modul_VHDL.vhd
ddr2_sdram/trunk/Top_Modul_VHDL_bitgen.xwbt
ddr2_sdram/trunk/UB_Clock_UCF.ucf
ddr2_sdram/trunk/Top_Modul_VHDL_guide.ncd
ddr2_sdram/trunk/DDR2_liesmich.txt
ddr2_sdram/trunk/UB_Y-Led_UCF.ucf
ddr2_sdram/trunk/UB_Taster_BUS_UCF.ucf
ddr2_sdram/trunk/Prj_12_DDR2.gise
ddr2_sdram/trunk/iseconfig/
ddr2_sdram/trunk/iseconfig/Prj_12_DDR2.projectmgr
ddr2_sdram/trunk/iseconfig/Top_Modul_VHDL.xreport
ddr2_sdram/trunk/MIG_Settings/
ddr2_sdram/trunk/MIG_Settings/m02_Create_Design.JPG
ddr2_sdram/trunk/MIG_Settings/b01_part.JPG
ddr2_sdram/trunk/MIG_Settings/m08_Pins.JPG
ddr2_sdram/trunk/MIG_Settings/m07_Options2.JPG
ddr2_sdram/trunk/MIG_Settings/m05_Controller.JPG
ddr2_sdram/trunk/MIG_Settings/m11_License.JPG
ddr2_sdram/trunk/MIG_Settings/m03_FPGAs.JPG
ddr2_sdram/trunk/MIG_Settings/m06_Options.JPG
ddr2_sdram/trunk/MIG_Settings/b02_generation.JPG
ddr2_sdram/trunk/MIG_Settings/m04_Memory.JPG
ddr2_sdram/trunk/MIG_Settings/b04_mig_361.JPG
ddr2_sdram/trunk/MIG_Settings/m13_Design.JPG
ddr2_sdram/trunk/MIG_Settings/m10_Summary.JPG
ddr2_sdram/trunk/MIG_Settings/m01_customize.JPG
ddr2_sdram/trunk/MIG_Settings/m09_Bank.JPG
ddr2_sdram/trunk/MIG_Settings/m14_Coregen_Readme.JPG
ddr2_sdram/trunk/MIG_Settings/m12_PCB.JPG
ddr2_sdram/trunk/MIG_Settings/b03_advanced.JPG
ddr2_sdram/trunk/Prj12_Impact.ipf
ddr2_sdram/trunk/Prj12_Impact_xdb/
ddr2_sdram/trunk/Prj12_Impact_xdb/tmp/
ddr2_sdram/trunk/DDR2_Control_VHDL.vhd
ddr2_sdram/trunk/impact_impact.xwbt
ddr2_sdram/trunk/Buttons_VHDL.vhd
ddr2_sdram/trunk/webtalk_impact.xml
ddr2_sdram/trunk/DDR2_Read_VHDL.vhd
ddr2_sdram/trunk/_xmsgs/
ddr2_sdram/trunk/Prj_12_DDR2.xise
ddr2_sdram/trunk/UB_Schalter_BUS_UCF.ucf
ddr2_sdram/trunk/ipcore_dir/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_tap_dly.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_dqs_delay_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_rd_gray_cntr.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_parameters_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_controller_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_0_wr_en_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_write_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dq_iob.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_wr_gray_cntr.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_

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