- z_fail_volume Demonstrate Z
- R61505W Renesas IC initialization code for TFT LCD. 262K
- Final This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex
- slide-mode-of-dc-motor sliding mode control of dc motor
- ise 这个是主要以picoblaze 为核心的串口
- paycalculator 卡耐基梅隆大学SSD3 practical quiz1的答案
文件名称:PC-CFR
-
所属分类:
- 标签属性:
- 上传时间:2015-11-12
-
文件大小:2.49mb
-
已下载:11次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
采用matlab simulink编写的消峰参考设计,可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比,提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier efficiency.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pc_cfr_test_v3_1c.m
testcase1.mat
pc_cfr_virtex4_v1_1_cw_bd.bmm
pc_cfr_virtex4_v1_1_cw.bit
pc_cfr_virtex4_v1_1.mdl
pc_cfr_virtex5_v1_1.mdl
pc_cfr_virtex5_v1_1_cw_bd.bmm
pc_cfr_virtex5_v1_1_cw.bit
pc_cfr_virtex5_v1_1_hwl.mdl
pc_cfr_virtex4_v1_1_hwl.mdl
ccdf.p
cfr_iteration_v42.p
cordic_abs_sin_cos.p
dec2tce.p
sigprops.p
simple_abs.p
tc_round.p
tce2dec.p
readme_xapp1033.txt
check_pc_cfr_v1.m
testcase1.mat
pc_cfr_virtex4_v1_1_cw_bd.bmm
pc_cfr_virtex4_v1_1_cw.bit
pc_cfr_virtex4_v1_1.mdl
pc_cfr_virtex5_v1_1.mdl
pc_cfr_virtex5_v1_1_cw_bd.bmm
pc_cfr_virtex5_v1_1_cw.bit
pc_cfr_virtex5_v1_1_hwl.mdl
pc_cfr_virtex4_v1_1_hwl.mdl
ccdf.p
cfr_iteration_v42.p
cordic_abs_sin_cos.p
dec2tce.p
sigprops.p
simple_abs.p
tc_round.p
tce2dec.p
readme_xapp1033.txt
check_pc_cfr_v1.m
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.