文件名称:CRC
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- 上传时间：2015-12-12
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文件大小：206.38kb
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赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and
correctness. This application note shows how to implement Configurable CRC Modules with
LocalLink interfaces. Users tailor the module features to suit the protocol or application
implemented in their system. The user-specified options for each of the configurable features
are input parameters to the VHDL code for the modules. The VHDL source files for the CRC
modules are coded using generate statements. The modules have two LocalLink interfaces: an
upstream interface (US) and a downstream interface (DS)
correctness. This application note shows how to implement Configurable CRC Modules with
LocalLink interfaces. Users tailor the module features to suit the protocol or application
implemented in their system. The user-specified options for each of the configurable features
are input parameters to the VHDL code for the modules. The VHDL source files for the CRC
modules are coded using generate statements. The modules have two LocalLink interfaces: an
upstream interface (US) and a downstream interface (DS)
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下载文件列表
CRC校验参考设计2.pdf
xapp562/
xapp562/faq
xapp562/readme
xapp562/src/
xapp562/src/vhdl/
xapp562/src/vhdl/crc_components_pkg.vhd
xapp562/src/vhdl/crc_functions_pkg.vhd
xapp562/src/vhdl/crc_gen.vhd
xapp562/src/vhdl/crc_valid_gen_rx.vhd
xapp562/src/vhdl/data_ds_modules.vhd
xapp562/src/vhdl/rem_ds_modules.vhd
xapp562/src/vhdl/rxcrc.vhd
xapp562/src/vhdl/rx_crc_example.vhd
xapp562/src/vhdl/state_machine_rx.vhd
xapp562/src/vhdl/state_machine_tx.vhd
xapp562/src/vhdl/txcrc.vhd
xapp562/src/vhdl/tx_crc_example.vhd
xapp562/synth/
xapp562/synth/rxcrc.prj
xapp562/synth/rxcrc_xst.files
xapp562/synth/rxcrc_xst.scr
xapp562/synth/txcrc.prj
xapp562/synth/txcrc_xst.files
xapp562/synth/txcrc_xst.scr
xapp562/test/
xapp562/test/func_sim/
xapp562/test/func_sim/stim/
xapp562/test/func_sim/stim/stimfile_list
xapp562/test/func_sim/stim/tt_001.dat
xapp562/test/func_sim/stim/tt_002.dat
xapp562/test/func_sim/stim/tt_003.dat
xapp562/test/func_sim/stim/tt_004.dat
xapp562/test/func_sim/stim/tt_005.dat
xapp562/test/func_sim/stim/tt_006.dat
xapp562/test/func_sim/stim/tt_007.dat
xapp562/test/func_sim/stim/tt_008.dat
xapp562/test/func_sim/stim/tt_009.dat
xapp562/test/func_sim/stim/tt_010.dat
xapp562/test/func_sim/vhdl_sim.do
xapp562/test/func_sim/wave.do
xapp562/test/src/
xapp562/test/src/vhdl/
xapp562/test/src/vhdl/crc_tb.vhd
xapp562/test/src/vhdl/ll_stim.vhd
xapp562/
xapp562/faq
xapp562/readme
xapp562/src/
xapp562/src/vhdl/
xapp562/src/vhdl/crc_components_pkg.vhd
xapp562/src/vhdl/crc_functions_pkg.vhd
xapp562/src/vhdl/crc_gen.vhd
xapp562/src/vhdl/crc_valid_gen_rx.vhd
xapp562/src/vhdl/data_ds_modules.vhd
xapp562/src/vhdl/rem_ds_modules.vhd
xapp562/src/vhdl/rxcrc.vhd
xapp562/src/vhdl/rx_crc_example.vhd
xapp562/src/vhdl/state_machine_rx.vhd
xapp562/src/vhdl/state_machine_tx.vhd
xapp562/src/vhdl/txcrc.vhd
xapp562/src/vhdl/tx_crc_example.vhd
xapp562/synth/
xapp562/synth/rxcrc.prj
xapp562/synth/rxcrc_xst.files
xapp562/synth/rxcrc_xst.scr
xapp562/synth/txcrc.prj
xapp562/synth/txcrc_xst.files
xapp562/synth/txcrc_xst.scr
xapp562/test/
xapp562/test/func_sim/
xapp562/test/func_sim/stim/
xapp562/test/func_sim/stim/stimfile_list
xapp562/test/func_sim/stim/tt_001.dat
xapp562/test/func_sim/stim/tt_002.dat
xapp562/test/func_sim/stim/tt_003.dat
xapp562/test/func_sim/stim/tt_004.dat
xapp562/test/func_sim/stim/tt_005.dat
xapp562/test/func_sim/stim/tt_006.dat
xapp562/test/func_sim/stim/tt_007.dat
xapp562/test/func_sim/stim/tt_008.dat
xapp562/test/func_sim/stim/tt_009.dat
xapp562/test/func_sim/stim/tt_010.dat
xapp562/test/func_sim/vhdl_sim.do
xapp562/test/func_sim/wave.do
xapp562/test/src/
xapp562/test/src/vhdl/
xapp562/test/src/vhdl/crc_tb.vhd
xapp562/test/src/vhdl/ll_stim.vhd
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