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文件名称:2_digital_clock
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- 上传时间:2016-02-28
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文件大小:1.41mb
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采用Verilog HDL RTL 描述完成数字钟,基于basys3,软件平台:vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
(系统自动生成,下载前可以参看下载内容)
下载文件列表
采用Verilog HDL RTL 描述完成数字钟_v1.docx
digital_clock/
digital_clock/design_source/
digital_clock/design_source/bcd_counter.v
digital_clock/design_source/binbcd8.v
digital_clock/design_source/clk_1s.v
digital_clock/design_source/count_top.v
digital_clock/design_source/counter.v
digital_clock/design_source/display.v
digital_clock/design_source/seg7.v
digital_clock/xdc/
digital_clock/xdc/clock.xdc
digital_clock/
digital_clock/design_source/
digital_clock/design_source/bcd_counter.v
digital_clock/design_source/binbcd8.v
digital_clock/design_source/clk_1s.v
digital_clock/design_source/count_top.v
digital_clock/design_source/counter.v
digital_clock/design_source/display.v
digital_clock/design_source/seg7.v
digital_clock/xdc/
digital_clock/xdc/clock.xdc
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