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文件名称:cachecontroller_latest.tar
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- 上传时间：2016-08-22
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This project is to develop a direct mapped cache controller for embedded applications.
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cachecontroller/
cachecontroller/tags/
cachecontroller/branches/
cachecontroller/trunk/
cachecontroller/trunk/doc/
cachecontroller/trunk/doc/DirectMappedCacheController Specifications v0.1.dot
cachecontroller/trunk/backend/
cachecontroller/trunk/sim/
cachecontroller/trunk/sim/rtl_sim/
cachecontroller/trunk/sim/gate_sim/
cachecontroller/trunk/bench/
cachecontroller/trunk/bench/verilog/
cachecontroller/trunk/bench/vhdl/
cachecontroller/trunk/syn/
cachecontroller/trunk/syn/xilinx/
cachecontroller/trunk/syn/xilinx/run/
cachecontroller/trunk/syn/xilinx/bin/
cachecontroller/trunk/syn/xilinx/log/
cachecontroller/trunk/syn/xilinx/src/
cachecontroller/trunk/syn/xilinx/out/
cachecontroller/trunk/rtl/
cachecontroller/trunk/rtl/verilog/
cachecontroller/trunk/rtl/verilog/eight_to_one_mux_8bit.v
cachecontroller/trunk/rtl/verilog/one_to_eight_demux_8bit.v
cachecontroller/trunk/rtl/verilog/RAMB16_S8.v
cachecontroller/trunk/rtl/verilog/t_memory_bank.v
cachecontroller/trunk/rtl/verilog/memory_bank.v
cachecontroller/trunk/rtl/verilog/bufif0_8bit.v
cachecontroller/trunk/rtl/vhdl/
cachecontroller/trunk/sw/
cachecontroller/tags/
cachecontroller/branches/
cachecontroller/trunk/
cachecontroller/trunk/doc/
cachecontroller/trunk/doc/DirectMappedCacheController Specifications v0.1.dot
cachecontroller/trunk/backend/
cachecontroller/trunk/sim/
cachecontroller/trunk/sim/rtl_sim/
cachecontroller/trunk/sim/gate_sim/
cachecontroller/trunk/bench/
cachecontroller/trunk/bench/verilog/
cachecontroller/trunk/bench/vhdl/
cachecontroller/trunk/syn/
cachecontroller/trunk/syn/xilinx/
cachecontroller/trunk/syn/xilinx/run/
cachecontroller/trunk/syn/xilinx/bin/
cachecontroller/trunk/syn/xilinx/log/
cachecontroller/trunk/syn/xilinx/src/
cachecontroller/trunk/syn/xilinx/out/
cachecontroller/trunk/rtl/
cachecontroller/trunk/rtl/verilog/
cachecontroller/trunk/rtl/verilog/eight_to_one_mux_8bit.v
cachecontroller/trunk/rtl/verilog/one_to_eight_demux_8bit.v
cachecontroller/trunk/rtl/verilog/RAMB16_S8.v
cachecontroller/trunk/rtl/verilog/t_memory_bank.v
cachecontroller/trunk/rtl/verilog/memory_bank.v
cachecontroller/trunk/rtl/verilog/bufif0_8bit.v
cachecontroller/trunk/rtl/vhdl/
cachecontroller/trunk/sw/
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